Display apparatus and method for controlling display apparatus

Patent metadata

Field	Value
Publication number	US-11854479-B2
Application number	US-202117800976-A
Country	US
Kind code	B2
Filing date	Jan 8, 2021
Priority date	Feb 21, 2020
Publication date	Dec 26, 2023
Grant date	Dec 26, 2023

Abstract

A display apparatus including a plurality of pixel circuit rows, where each pixel circuit row includes a plurality of pixel circuits, and each pixel circuit includes a light emitting component and a driving circuit. A gate voltage generation circuit generates a plurality of scan signals. A first scan signal and a second scan signal respectively control write circuits in driving circuits in a first pixel circuit row and a second pixel circuit row. The write circuit adjusts, based on a data voltage for controlling luminance of a light emitting component, a voltage at one end of a storage capacitor to a first voltage. The first scan signal further controls a reset circuit in a driving circuit in a second pixel circuit row, and the reset circuit resets the voltage at one end of the storage capacitor to a second voltage based on a reference voltage.

First claim

What is claimed is:

1. A display apparatus, comprising:
pixel circuit rows comprising a first pixel circuit row and a second pixel circuit row, wherein each of the pixel circuit rows comprises pixel circuits, and wherein each of the pixel circuits comprises:
a light emitting component configured to emit light; and
a driving circuit configured to drive the light emitting component and comprising:
a storage capacitor;
a write circuit configured to adjust, based on a data voltage, a first voltage at one end of the storage capacitor to a second voltage, wherein the data voltage controls luminance of the light; and
a reset circuit configured to reset, based on a reference voltage, the second voltage to a third voltage; and

a gate voltage generation circuit coupled to the pixel circuit rows and configured to:
generate a first scan signal to control first write circuits in the first pixel circuit row and control first reset circuits in the second pixel circuit row, wherein the first scan signal starts to be loaded by the first pixel circuit row at a first moment and starts to be loaded by the second pixel circuit row at a second moment; and
generate a second scan signal to control second write circuits in the second pixel circuit row,

wherein the second scan signal starts to be loaded by the second pixel circuit row at the second moment,
wherein in a same frame scan cycle, the first moment is earlier than the second moment by a first odd multiple of a clock cycle, and
wherein the first odd multiple is greater than or equal to 3.

2. The display apparatus of claim 1 , wherein the second pixel circuit row is configured to load the first scan signal and the second scan signal in a time period, wherein in the time period, a third moment of a first initial low electrical level of the first scan signal is earlier than a fourth moment of a second initial low electrical level of the second scan signal by a second odd multiple of the clock cycle, and wherein the second odd multiple is greater than or equal to 3.

3. The display apparatus of claim 1 , wherein the second pixel circuit row is configured to load the first scan signal and the second scan signal in a time period, wherein in the time period, a third moment of a first initial high electrical level of the first scan signal is earlier than a fourth moment of a second initial high electrical level of the second scan signal by a second odd multiple of the clock cycle, and wherein the second odd multiple is greater than or equal to 3.

4. The display apparatus according to claim 1 , wherein the driving circuit comprises seven transistors and one storage capacitor.

5. The display apparatus according to claim 1 , wherein the write circuit comprises:
a first transistor comprising:
a first source electrode, wherein a first source voltage of the first source electrode is controlled by the data voltage;
a first gate electrode, wherein a first gate voltage of the first gate electrode is controlled by the first scan signal or the second scan signal; and
a first drain electrode;

a second transistor comprising:
a second source electrode coupled to the first drain electrode;
a second gate electrode coupled to the one end of the storage capacitor; and
a second drain electrode; and

a third transistor comprising:
a third source electrode coupled to the second drain electrode;
a third gate electrode, wherein a second gate voltage of the third gate electrode is controlled by the first scan signal or the second scan signal; and
a third drain electrode coupled to the second gate electrode and the one end of the storage capacitor.

6. The display apparatus of claim 5 , wherein the second voltage is equal to a sum of a threshold voltage of the second transistor and a difference between the data voltage and a fourth voltage between the first source electrode and the first drain electrode.

7. The display apparatus of claim 1 , wherein the reset circuit comprises a transistor, and wherein the transistor comprises:
a gate electrode controlled by the first scan signal;
a source electrode controlled by the reference voltage; and
a drain electrode coupled to the one end of the storage capacitor.

8. The display apparatus of claim 7 , wherein the third voltage is equal to a difference between the reference voltage and a fourth voltage between the source electrode and the drain electrode.

9. The display apparatus of claim 1 , wherein each light emitting component comprises:
at least one of an organic light-emitting diode (OLED) or a light-emitting diode (LED);
a self-capacitor connected in parallel with the at least one of the OLED or the and the LED.

10. A method for controlling a display apparatus, wherein the method comprises:
generating a first scan signal and a second scan signal;
loading the first scan signal to first write circuits in first driving circuits in a first pixel circuit row and to reset circuits in second driving circuits in a second pixel circuit row, wherein the first scan signal starts to be loaded to the first pixel circuit row at a first moment, and wherein the first scan signal starts to be loaded to the second pixel circuit row at a second moment;
loading the second scan signal to second write circuits in the second driving circuits, wherein the second scan signal starts to be loaded to the second pixel circuit row at the second moment;
adjusting, based on a data voltage, a first voltage at one end of a storage capacitor in each of the first driving circuits and the second driving circuits to a second voltage, wherein the data voltage controls luminance of light emitted by light emitting components in the first pixel circuit row and the second pixel circuit row; and
resetting, based on a reference voltage, the first voltage to a third voltage,
wherein in a same frame scan cycle, the first moment is earlier than the second moment by a first odd multiple of a clock cycle, and
wherein the first odd multiple is greater than or equal to 3.

11. The method of claim 10 , wherein loading the first scan signal to the reset circuits and loading the second scan signal to the second write circuits comprise loading the first scan signal to the reset circuits and loading the second scan signal to the second write circuits in a time period such that a third moment of a first initial low electrical level of the first scan signal is earlier than a fourth moment of a second initial low electrical level of the second scan signal by a second odd multiple of the clock cycle, and wherein the second odd multiple is greater than or equal to 3.

12. The method of claim 10 , wherein loading the first scan signal to the reset circuits and loading the second scan signal to the second write circuits comprise loading the first scan signal to the reset circuits and loading the second scan signal to the second write circuits in a time period such that a third moment of a first initial high electrical level of the first scan signal is earlier than a fourth moment of a second initial high electrical level of the second scan signal by a second odd multiple of the clock cycle, and wherein the second odd multiple is greater than or equal to 3.

13. The method of claim 10 , wherein each write circuit in the first write circuits and the second write circuits comprises a first transistor, a second transistor, and a third transistor, and wherein the method further comprises:
controlling a first gate voltage of the first transistor by using the first scan signal or the second scan signal;
controlling a source voltage of the first transistor by using the data voltage;
coupling a first source electrode of the second t

Assignees

• Huawei Tech Co Ltd

Inventors

• Ouyang Shiangruei
• He Haiming

Classifications

• G09G3/3233 Primary

  with pixel circuitry controlling the current through the light-emitting element · CPC title

• G09G2300/0842

  forming a memory circuit, e.g. a dynamic memory with one capacitor · CPC title

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title

• G09G2320/0233

  Improving the luminance or brightness uniformity across the screen · CPC title

• G09G2320/0626

  for control of overall brightness · CPC title