Securing data stored in a memory of an IoT device during a low power mode

Patent metadata

Field	Value
Publication number	US-11853465-B2
Application number	US-202318095593-A
Country	US
Kind code	B2
Filing date	Jan 11, 2023
Priority date	Aug 24, 2018
Publication date	Dec 26, 2023
Grant date	Dec 26, 2023

Abstract

The disclosure relates to a method for enabling the secure functions of a chipset (1) and especially the encryption of the content of the secure memory (7) when the device goes into low power mode. The content of the secure memory (7) may be encrypted and stored in an external memory (20) during low power mode of the chipset (1).

First claim

The invention claimed is:

1. A method of securing a memory content of a first memory of a secure part of a chipset during a low power mode, wherein the low power mode causes the memory content to be erased from the first memory, comprising:
when entering the low power mode, encrypting and signing at least a part of the memory content to obtain an encrypted memory content and storing the encrypted memory content in an external memory external to the secure part during the low power mode.

2. The method according to claim 1 , further comprising:
when exiting the low power mode, receiving in the secure part the encrypted memory content from the external memory, decrypting and authenticating the encrypted memory content to obtain decrypted memory content, and loading the decrypted memory content in the first memory.

3. The method according to claim 2 , wherein the chipset is configured to:
set up a secure link between the secure part and a remote client access server;
receive a secure stamp from the client access server in the secure part via the secure link, wherein the secure stamp comprises data for securing the memory content;
store the secure stamp in a second memory of the secure part, wherein the secure stamp remains stored in the second memory in the low power mode;
when entering the low power mode, encrypt the at least part of the content using the secure stamp; and
when exiting the low power mode, decrypt the encrypted memory content using the secure stamp.

4. The method according to claim 3 , wherein the method comprises removing by the chipset, the secure stamp from the second memory when the encrypted memory content is decrypted.

5. The method according to claim 3 , wherein the method comprises receiving a new secure stamp received after setting up of the secure link between the client access server, and the secure part being different from a previous secure stamp.

6. The method according to claim 3 , wherein the method comprises implementing the secure link between the client access server and the secure part using a Diffie-Hellman key exchange protocol.

7. The method according to claim 3 , wherein the method comprises using a timestamp as secure stamp.

8. The method according to claim 3 , wherein the method comprises encrypting, by the secure part, the memory content of the first memory based on a cryptographic algorithm using the secure stamp as an initialization vector to the cryptographic algorithm.

9. The method according to claim 2 , wherein the method comprises using the secure part as part of a trusted execution environment of the chipset.

10. The method according to claim 9 , wherein the method comprises controlling, by the trusted execution environment, the storing of the encrypted memory content in the external memory when entering low power mode and controlling the loading of the encrypted memory content in the secure part when exiting low power mode.

11. The method according to claim 9 , further comprising:
the secure part generating a random key;
when entering the low power mode, the trusted execution environment-encrypting computer code running in the trusted execution environment using the random key as cryptographic key and the secure stamp as initialization vector to obtain encrypted computer code; and
when exiting low power mode, the trusted execution environment decrypting the encrypted computer code using the random key as cryptographic key and the secure stamp as initialization vector.

12. The method according to claim 11 , further comprising storing the random key in the second memory.

13. The method according to claim 11 , wherein the method comprises communicatively connecting with a further secure link, the secure part to the trusted execution environment, the further secure link using a random shared key for cryptographically securing the further secure link.

14. The method according to claim 13 , wherein the method comprises binding the random key to the secure stamp by the random shared key.

15. The method according to claim 13 , wherein the method comprises re-initializing the further secure link after each low power mode with a new random shared key.

16. A device comprising a processor configured to perform the steps of the method according to claim 1 .

17. A computer-readable non-transitory storage medium comprising computer executable instructions which, when executed by a processor, cause the processor to carry out the steps of the method according to claim 1 .

Assignees

• Nagravision Sarl

Inventors

• Hunacek Didier
• Macchetti Marco
• Perrine Jerome

Classifications

• G06F21/72 Primary

  in cryptographic circuits · CPC title

• G06F1/3275

  Power saving in memory, e.g. RAM, cache · CPC title

• G06F21/602

  Providing cryptographic facilities or services · CPC title

• G06F21/81

  by operating on the power supply, e.g. enabling or disabling power-on, sleep or resume operations · CPC title

• H04L9/0841

  involving Diffie-Hellman or related key agreement protocols · CPC title