Wafer structure

Patent metadata

Field	Value
Publication number	US-11850854-B2
Application number	US-202117473276-A
Country	US
Kind code	B2
Filing date	Sep 13, 2021
Priority date	Nov 24, 2020
Publication date	Dec 26, 2023
Grant date	Dec 26, 2023

Abstract

A wafer structure is disclosed and includes a chip substrate and an inkjet chip. The chip substrate is a silicon substrate fabricated by a semiconductor process on a wafer of 12 inches. The inkjet chips are formed on the chip substrate by the semiconductor process and diced into the inkjet chip. The inkjet chip includes plural ink-drop generators generated by the semiconductor process on the chip substrate. Each of the plurality of ink-drop generators includes a nozzle. A diameter of the nozzle is in a range between 0.5 micrometers and 10 micrometers. A volume of an inkjet drop discharged from the nozzle is in a range between 1 femtoliter and 3 picoliters. The ink-drop generators form plural longitudinal axis array groups having a pitch and plural horizontal axis array groups having a central stepped pitch equal to or less than 1/600 inches.

First claim

What is claimed is:

1. A wafer structure, comprising:
a chip substrate, which is a silicon substrate, fabricated by a semiconductor process on a wafer of at least 12 inches; and
at least one inkjet chip directly formed on the chip substrate by the semiconductor process and diced into at least one inkjet chip for inkjet printing,
wherein the at least one inkjet chip includes:
at least one ink-supply channel configured to provide ink; and
a plurality of ink-drop generators produced by the semiconductor process on the chip substrate and respectively connected to the at least one ink-supply channel,

wherein each of the plurality of ink-drop generators comprises a thermal-barrier layer, a resistance heating layer, only one conductive layer, a protective layer, a barrier layer, an ink-supply chamber and a nozzle, wherein the conductive layer and a part of the protective layer are formed on the resistance heating layer, a rest part of the protective layer is formed on the conductive layer, the barrier layer is directly formed on the protective layer, the ink-supply chamber and the nozzle are integrally formed in the barrier layer, the ink-supply chamber has a bottom in communication with the protective layer, and a top in communication with the nozzle,
wherein a diameter of the nozzle is in a range between 0.5 micrometers and 10 micrometers, and a volume of an inkjet drop discharged from the nozzle is in a range between 1 femtoliter and 3 picoliters,
wherein in the at least one inkjet chip, the plurality of ink-drop generators are arranged in a longitudinal direction to form a plurality of longitudinal axis array groups having a pitch maintained between two adjacent ink-drop generators in the longitudinal direction,
wherein the barrier layer includes two opposite inner sidewalls defining two opposite sides of the ink-supply chamber, each of the two opposite inner sidewalls of the barrier layer continuously extends from a respective one of two opposite sides of a top surface of a continuous portion of the protective layer toward the nozzle, the two opposite inner sidewalls of the barrier layer entirely and directly overlap with the conductive layer in a direction normal to the bottom of the ink-supply chamber, and the top surface of the continuous portion of the protective layer is the bottom of the ink-supply chamber, and
wherein an ink supply path is formed between the at least one ink-supply channel and the ink-supply chamber of each of the plurality of ink-drop generators, and the ink supply path is configured to supply the ink from the at least one ink-supply channel to the ink-supply chamber in a plane parallel with the bottom of the ink supply chamber.

2. The wafer structure according to claim 1 , wherein the chip substrate is fabricated by the semiconductor process on a 12-inch wafer.

3. The wafer structure according to claim 1 , wherein the chip substrate is fabricated by the semiconductor process on a 16-inch wafer.

4. The wafer structure according to claim 1 , wherein the thermal-barrier layer is formed on the chip substrate, the resistance heating layer is formed on the thermal-barrier layer.

5. The wafer structure according to claim 1 , further comprising a conductor connected by the conductive layer fabricated by the semiconductor process of equal to or less than 90 nanometers to form an inkjet control circuit.

6. The wafer structure according to claim 5 , wherein the conductor connected by the conductive layer is fabricated by the semiconductor process of 2 nanometers to 90 nanometers to form an inkjet control circuit.

7. The wafer structure according to claim 1 , wherein the inkjet chip has a printing swath equal to or more than at least 0.25 inches, and the inkjet chip has a width ranging from at least 0.5 mm to 10 mm.

8. The wafer structure according to claim 7 , wherein the printing swath of the inkjet chip ranges from at least 0.25 inches to 1.25 inches.

9. The wafer structure according to claim 7 , wherein the printing swath of the inkjet chip ranges from at least 1.25 inches to 12 inches.

10. The wafer structure according to claim 7 , wherein the printing swath of the inkjet chip is at least 12 inches.

11. The wafer structure according to claim 7 , wherein the printing swath of the inkjet chip is 8.3 inches.

12. The wafer structure according to claim 7 , wherein the printing swath of the inkjet chip is 11.7 inches.

13. The wafer structure according to claim 1 , wherein in the at least one inkjet chip, the plurality of ink-drop generators are arranged in a horizontal direction to form a plurality of horizontal axis array groups having a central stepped pitch maintained between two adjacent ink-drop generators in the horizontal direction, wherein the central stepped pitch is at least equal to 1/600 inches or less.

14. The wafer structure according to claim 13 , wherein the central stepped pitch is equal to at least 1/600 inches to 1/1200 inches.

15. The wafer structure according to claim 14 , wherein the central stepped pitch is equal to 1/720 inches.

16. The wafer structure according to claim 13 , wherein the central stepped pitch is equal to at least 1/1200 inches to 1/2400 inches.

17. The wafer structure according to claim 13 , wherein the central stepped pitch is equal to at least 1/2400 inches to 1/24000 inches.

18. The wafer structure according to claim 13 , wherein the central stepped pitch is equal to at least 1/24000 inches to 1/48000 inches.

19. A wafer structure, comprising:
a chip substrate, which is a silicon substrate, fabricated by a semiconductor process on a wafer of at least 12 inches; and
at least one inkjet chip directly formed on the chip substrate by the semiconductor process and diced into at least one inkjet chip for inkjet printing,
wherein the at least one inkjet chip includes a plurality of ink-drop generators produced by the semiconductor process on the chip substrate, and each of the plurality of ink-drop generators comprises a nozzle, wherein a diameter of the nozzle is in a range between 0.5 micrometers and 10 micrometers, and a volume of an inkjet drop discharged from the nozzle is in a range between 1 femtoliter and 3 picoliters,
wherein in the at least one inkjet chip, the plurality of ink-drop generators are arranged in a longitudinal direction to form a plurality of longitudinal axis array groups having a pitch maintained between two adjacent ink-drop generators in the longitudinal direction,
wherein each of the ink-drop generators comprises a thermal-barrier layer, a resistance heating layer, a conductive layer, a protective layer, a barrier layer and an ink-supply chamber, wherein the thermal-barrier layer is formed on the chip substrate, the resistance heating layer is formed on the thermal-barrier layer, the conductive layer and a part of the protective layer are formed on the resistance heating layer, a rest part of the protective layer is formed on the conductive layer, the barrier layer is formed on the protective layer, and the ink-supply chamber and the nozzle are integrally formed in the barrier layer, wherein the ink-supply chamber has a bottom in communication with the protective layer, and a top in communication with the nozzle, and
wherein each of the first inkjet chip and the second inkjet chip comprises at least one ink-supply channel and a plurality of manifolds fabricated by the semiconductor process, wherein the ink-supply channel provides ink, and the ink-supply channel is in communication with the plurality of the manifolds, wherein the plurality of manifolds are i

Assignees

• Microjet Technology Co Ltd

Inventors

• Mou Hao-Jan
• Chang Ying-Lun
• Tai Hsien-Chung
• Han Yung-Lung
• Huang Chi-Feng
• Lee Wei-Ming

Classifications

• B41J2/14145 Primary

  Structure of the manifold · CPC title

• B41J2/14072

  Electrical connections, e.g. details on electrodes, connecting the chip to the outside... · CPC title

• B41J2202/11

  characterised by specific geometrical characteristics · CPC title

• B41J2/14 Primary

  Structure thereof {only for on-demand ink jet heads} · CPC title

• B41J2/04541 Primary

  Specific driving circuit · CPC title