Audio non-linearity cancellation for switches for audio and other applications

Patent metadata

Field	Value
Publication number	US-11848696-B2
Application number	US-202217974030-A
Country	US
Kind code	B2
Filing date	Oct 26, 2022
Priority date	May 18, 2021
Publication date	Dec 19, 2023
Grant date	Dec 19, 2023

Abstract

An aspect includes an apparatus including a first amplifier; a first field effect transistor (FET) including a first source coupled to an output of the first amplifier, and a first drain for coupling to a first load; and a first gate drive circuit including an input coupled to the output of the first amplifier and an output coupled to a first gate of the first FET. Another aspect includes a method including amplifying a first audio signal using a first audio amplifier to generate a first voltage; generating a first gate voltage based on the first voltage; applying the first gate voltage to a first gate of a first field effect transistor (FET) coupled between the first audio amplifier and a first audio transducer; and applying the first voltage to a first source of the first FET.

First claim

What is claimed:

1. An apparatus, comprising:
a first amplifier configured to generate a first voltage;
a first field effect transistor (FET) including a first source coupled to an output of the first amplifier, and a first drain for coupling to a first load; and
a first gate drive circuit configured to generate a first gate voltage for a first gate of the first FET, wherein the first gate voltage is based on the first voltage.

2. The apparatus of claim 1 , wherein the first gate drive circuit comprises a voltage scaling device configured to scale the first voltage to generate a second voltage, wherein the first gate voltage is based on the second voltage.

3. The apparatus of claim 1 , wherein the first gate drive circuit comprises:
a voltage scaling device configured to scale the first voltage to generate a second voltage; and
a voltage summer configured to sum the second voltage with a direct current (DC) voltage to generate the first gate voltage for the first gate of the first FET.

4. The apparatus of claim 3 , wherein the voltage scaling device comprises:
first and second resistors coupled in series between the output of the first amplifier and a voltage rail; and
a difference amplifier including a first input coupled to the output of the first amplifier, a second input coupled to a node between the first and second resistors, and an output coupled to the first gate of the first FET.

5. The apparatus of claim 1 , wherein the first amplifier comprises an input configured to receive an analog audio signal.

6. The apparatus of claim 1 , wherein the first load comprises an audio transducer.

7. The apparatus of claim 1 , further comprising a Universal Serial Bus (USB) port coupled between the first FET and the first load.

8. The apparatus of claim 1 , further comprising:
a second amplifier configured to generate a second voltage;
a second field effect transistor (FET) including a second source coupled to an output of the second amplifier, and a second drain for coupling to a second load; and
a second gate drive circuit configured to generate a second gate voltage for a second gate of the second FET, wherein the second gate voltage is based on the second voltage.

9. The apparatus of claim 8 , wherein the second gate drive circuit comprises a voltage scaling device configured to scale the second voltage to generate a third voltage, wherein the second gate voltage is based on the third voltage.

10. The apparatus of claim 8 , wherein the second gate drive circuit comprises:
a voltage scaling device configured to scale the second voltage to generate a third voltage; and
a voltage summer configured to sum the third voltage with a direct current (DC) voltage to generate the second gate voltage for the second gate of the second FET.

11. The apparatus of claim 8 , further comprising:
a third field effect transistor (FET) including a third source coupled to a voltage rail, and a third drain for coupling to the first and second loads; and
a third gate drive circuit configured to generate a third gate voltage for a third gate of the third FET, wherein the third gate voltage is based on the first and second voltages.

12. The apparatus of claim 11 , wherein the third gate drive circuit comprises:
a first voltage summer configured to generate a third voltage based on a sum of the first and second voltages;
a voltage scaling device configured to scale the third voltage to generate a fourth voltage; and
a second voltage summer configured to sum the fourth voltage with a direct current (DC) voltage to generate the third gate voltage for to the third gate of the third FET.

13. The apparatus of claim 12 , wherein the first voltage summer comprises a summing amplifier including a first input coupled to the output of the first amplifier, and a second input coupled to the output of the second amplifier, and wherein the voltage scaling device comprises:
first and second resistors coupled in series between an output of the summing amplifier and a voltage rail; and
a difference amplifier including a first input coupled to the output of the summing amplifier, a second input coupled to a node between the first and second resistors, and an output coupled to the third gate of the third FET.

14. The apparatus of claim 1 , further comprising a first bulk drive circuit configured to generate a first bulk voltage for a first bulk of the first FET, wherein the first bulk voltage is based on the first voltage.

15. The apparatus of claim 14 , wherein the first bulk drive circuit comprises a voltage scaling device.

16. The apparatus of claim 14 , further comprising:
a second amplifier configured to generate a second voltage;
a second field effect transistor (FET) including a second source coupled to an output of the second amplifier, and a second drain for coupling to a second load; and
a second gate drive circuit configured to generate a second gate voltage for a second gate of the second FET, wherein the second gate voltage is based on the second voltage.

17. The apparatus of claim 16 , further comprising a second bulk drive circuit configured to generate a second bulk voltage for a second bulk of the second FET, wherein the second bulk voltage is based on the second voltage.

18. The apparatus of claim 17 , wherein the second bulk drive circuit comprises a voltage scaling device.

19. The apparatus of claim 17 , further comprising:
a third field effect transistor (FET) including a third source coupled to a voltage rail, and a third drain for coupling to the first and second loads; and
a third gate drive circuit configured to generate a third gate voltage for a third gate of the third FET, wherein the third gate voltage is based on the first and second voltages.

20. The apparatus of claim 19 , further comprising a third bulk drive circuit configured to generate a third bulk voltage for a third bulk of the third FET, wherein the third bulk voltage is based on the first and second voltages.

21. The apparatus of claim 20 , wherein the third bulk drive circuit comprises:
a voltage summer configured to generate a third voltage based on a sum of the first and second voltages; and
a voltage scaling device configured to scale the third voltage to generate the third bulk voltage for the third bulk of the third FET.

22. A wireless communication device, comprising:
at least one antenna;
a transceiver coupled to the at least one antenna;
at least one digital signal processing core coupled to the transceiver;
a port configured to connect to one of at least one audio transducer and a digital data device;
at least one audio amplifier configured to generate at least one voltage;
at least one field effect transistor (FET) including a source coupled to an output of the at least one audio amplifier, respectively, and a drain coupled to the port; and
at least one gate drive circuit configured to generate at least one gate voltage for at least one gate of the at least one FET, wherein the at least one gate voltage is based on the at least one voltage.

23. The wireless communication device of claim 22 , wherein:
the at least one audio amplifier comprises first and second audio amplifiers configured to generate first and second voltages, respectively;
the at least one field effect transistor (FET) comprises first and second FETs; and
the at least one gate drive circuit comprises first and second gate drive circuits configured to generate the at least one gate v

Assignees

• Qualcomm Inc

Inventors

• YADAV Kshitij
• Dhanasekaran Vijayakumar

Classifications

• H04B1/40 Primary

  Circuits · CPC title

• H03F3/185

  with field-effect devices (H03F3/187 takes precedence) · CPC title

• H03F3/193

  with field-effect devices (H03F3/195 takes precedence) · CPC title

• H03F2200/03

  the amplifier being designed for audio applications · CPC title

• H03F2200/451

  the amplifier being a radio frequency amplifier · CPC title