Polarization controlled transistor

Patent metadata

Field	Value
Publication number	US-11848371-B2
Application number	US-202016920249-A
Country	US
Kind code	B2
Filing date	Jul 2, 2020
Priority date	Jul 2, 2020
Publication date	Dec 19, 2023
Grant date	Dec 19, 2023

Abstract

A transistor includes a first layer comprising a group III-nitride semiconductor. A second layer comprising a group III-nitride semiconductor is disposed over the first layer. A third layer comprising a group III-nitride semiconductor is disposed over the second layer. An interface between the second layer and the third layer form a polarization heterojunction. A fourth layer comprising a group III-nitride semiconductor is disposed over the third layer. An interface between the third layer and the fourth layer forms a pn junction. A first electrical contact pad is disposed on the fourth layer. A second electrical contact pad is disposed on the third layer. A third electrical contact pad is electronically coupled to bias the polarization heterojunction.

First claim

The invention claimed is:

1. A transistor comprising:
a first layer comprising a first group III-nitride semiconductor, wherein the first layer is a low doped drift region having a doping less than 1×10 17 cm −3 and a thickness greater than 5 μm;
a second layer comprising a second group III-nitride semiconductor having a first surface disposed over and in physical contact with the first layer, a second surface of the second layer being opposed to the first surface of the second layer;
a third layer comprising a third group III-nitride semiconductor, a first surface of the third layer disposed over and in physical contact with the second surface of the second layer, a second surface of the third layer being opposed to the first surface of the third layer, an interface between the second layer and the third layer forming a polarization heterojunction;
a fourth layer comprising a fourth group III-nitride semiconductor disposed over and in physical contact with the second surface of the third layer, an interface between the third layer and the fourth layer forming a pn junction;
a first electrical contact pad disposed on and in contact with the fourth layer;
a second electrical contact pad disposed on and in contact with the third layer; and
a third electrical contact pad electronically coupled to bias the polarization heterojunction;
wherein current flows vertically through the transistor from the first electrical contact pad to the third electrical contact pad when the transistor is in forward biased operation.

2. The transistor of claim 1 , wherein the second layer is n-doped, the third layer is n-doped and the fourth layer is p-doped.

3. The transistor of claim 2 , wherein a first doping concentration of the n-doped second and third layers is on the order of 10 17 to 10 19 cm −3 and a second doping concentration of the p-doped fourth layer is on the order of 10 18 to 10 20 cm −3 .

4. The transistor of claim 1 , wherein a distance between the pn junction and the polarization heterojunction is between 25 nm and 500 nm.

5. The transistor of claim 1 , wherein the second layer is an AlInN layer.

6. The transistor of claim 5 , wherein the third layer is a GaN layer.

7. The transistor of claim 6 , wherein the fourth layer is a second GaN layer.

8. The transistor of claim 5 , wherein the AlInN layer is an Al 1-x In x N layer, wherein x is between 0.05 and 0.30.

9. The transistor of claim 1 , wherein the second layer is an AlGaN layer.

10. The transistor of claim 9 , wherein:
the third layer is a GaN layer; and
the fourth layer is a second GaN layer.

11. The transistor of claim 10 , wherein the AlGaN layer is an Al y Ga 1-y N layer, wherein y is greater than 0.20.

12. The transistor of claim 1 , wherein a difference in polarization between the second and third layers at the polarization junction is greater than about 2×10 −2 C/m 2 .

13. The transistor of claim 1 , wherein a difference in polarization between the second and third layers at the polarization junction is greater than about 3×10 −2 C/m 2 .

14. The transistor of claim 1 , wherein the second layer is a quaternary AlGaInN layer.

15. The transistor of claim 1 , wherein a breakdown voltage between the second contact and the third contact exceeds 600 volts.

16. The transistor of claim 1 , wherein a maximum current through the transistor from the second contact to the third contact is greater than 10 amps.

17. The transistor of claim 1 , wherein the third electrical contact pad is disposed on a surface of the first layer opposite the second layer.

18. A circuit comprising:
a transistor that includes:
a first layer comprising a first group III-nitride semiconductor, wherein the first layer is a low doped drift region having a doping less than 1×10 17 cm −3 and a thickness greater than 5 μm;
a second layer comprising a second group III-nitride semiconductor having a first surface disposed over and in physical contact with the first layer, a second surface of the second layer being opposed to the first surface of the second layer;
a third layer comprising a third group III-nitride semiconductor, a first surface of the third layer disposed over and in physical contact with the second surface of the second layer, a second surface of the third layer being opposed to the first surface of the third layer, an interface between the second layer and the third layer forming a polarization heterojunction;
a fourth layer comprising a fourth group III-nitride semiconductor disposed over and in physical contact with the second surface of the third layer, an interface between the third layer and the fourth layer forming a pn junction;
a first electrical contact pad disposed on and in contact with the fourth layer;
a second electrical contact pad disposed on and in contact with the third layer;
a third electrical contact pad; and

a voltage source arranged to apply a voltage between the first contact pad and the second contact pad, the voltage controlling a current flowing between the second and third contact pads.

19. The circuit of claim 18 , wherein the second layer of the transistor is n-doped, the third layer of the transistor is n-doped and the fourth layer of the transistor is p-doped.

20. A method of making a transistor, comprising:
forming a second layer comprising a second group III-nitride semiconductor, a first surface of the second layer formed over and in physical contact with a first layer comprising a first group III-nitride semiconductor, a second surface of the second layer being opposed to the first surface of the second layer, wherein the first layer is a low doped drift region having a doping less than 1×10 17 cm −3 and a thickness greater than 5 μm;
forming a third layer comprising a third group III-nitride semiconductor over and in physical contact with the second surface of the second layer such that a polarization heterojunction is formed at an interface between the second layer and the third layer, a second surface of the third layer being opposed to a first surface of the third layer;
forming a fourth layer comprising a fourth group III-nitride semiconductor over and in physical contact with the second surface of the third layer such that a pn junction is formed at an interface between the third and fourth layers;
forming a first contact on and in contact with the fourth layer;
forming a second contact on and in contact with the third layer; and
forming a third contact electronically coupled to bias the polarization heterojunction.

Assignees

• Palo Alto Res Ct Inc
• Xerox Corp

Inventors

• Wunderer Thomas
• Lu Jengping
• Johnson Noble M

Classifications

• H10D62/8503

  Nitride Group III-V materials, e.g. AlN or GaN · CPC title

• H10D30/477 Primary

  Vertical HEMTs or vertical HHMTs · CPC title

• H10D30/4755

  having wide bandgap charge-carrier supplying layers, e.g. modulation doped HEMTs such as n-AlGaAs/GaAs HEMTs · CPC title

• H10D30/475

  having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs · CPC title

• H10D62/343

  Gate regions of field-effect devices having PN junction gates · CPC title