Memory integrated circuit with local amplifier module and local read-write conversion module to improve operation speed and reduce number of data lines

Patent metadata

Field	Value
Publication number	US-11848045-B2
Application number	US-202117396688-A
Country	US
Kind code	B2
Filing date	Aug 7, 2021
Priority date	Jun 19, 2020
Publication date	Dec 19, 2023
Grant date	Dec 19, 2023

Abstract

Embodiments of the present invention provide a semiconductor integrated circuit of a memory. The semiconductor integrated circuit can comprise a column selection module, a local read-write conversion module, and an amplifier module. The column selection module can be configured to couple a first data line to a bit line and couple a complementary data line to a complementary bit line. The local read-write conversion module can be configured to perform data transmission from at least one of the first data line or the first complementary data line to a second data line. The data transmission can occur during a memory read-write operation and in response to the local read-write conversion module receiving a read write control signal. The amplifier module can be configured to amplify data of the second data line based on a reference signal of a reference data line. The reference signal can serve as a reference for amplifying the data of the second data line.

First claim

What is claimed is:

1. A semiconductor integrated circuit of a memory, comprising:
a first data line coupled to a bit line through a column selection module, a first complementary data line coupled to a complementary bit line through the column selection module, a second data line, and a reference data line configured to provide a reference signal;
a local read-write conversion module configured to perform, during a memory read-write operation, in response to a read-write control signal, data transmission from at least one of the first data line or the first complementary data line to the second data line;
an amplifier module configured to amplify data of the second data line based on the reference signal of the reference data line, wherein the reference signal serves as a reference for amplifying the data of the second data line; and
a reference module to output the reference signal to the local read-write conversion module in response to receiving a read control signal of the read write control signal,
wherein the reference module is configured to reduce voltage potential of the reference signal during a memory read operation, and
wherein the local read-write conversion module is configured to reduce voltage potential of second data line during the memory read operation, wherein a discharge speed of the local read-write conversion module is greater than a discharge speed of the reference module.

2. The semiconductor integrated circuit of claim 1 , wherein the reference signal has a fixed voltage potential.

3. The semiconductor integrated circuit of claim 1 ,
wherein the reference module comprises at least one reference transistor.

4. The semiconductor integrated circuit of claim 3 , further comprising:
a reference control line configured to provide a reference control signal to the reference module, wherein the reference module outputs the reference signal to the local read-write conversion module in response to the reference control signal and the read control signal of the read write control signal.

5. The semiconductor integrated circuit of claim 4 , wherein:
the reference module includes a first port, a second port, a third port, and a fourth port;
the first port is coupled to the read control signal, the second port is coupled to the reference signal, the third port is coupled to a ground, and the fourth port coupled to the reference control signal; and
the reference module discharges the voltage potential of the of the reference signal during the memory read operation through the second port and the third port.

6. The semiconductor integrated circuit of claim 5 , wherein the reference module comprises a first switch unit and a second switch unit, wherein:
the first switch unit includes a first node and is coupled between the second switch unit and the ground, wherein the first switch unit is configured to form a conductive pathway between the first node to the third port in response to the reference module receiving the read control signal; and
the first switch unit includes a second node and is coupled between the second port and the fourth port, wherein the second switch unit is configured to form a conductive pathway between the second port and the second node in response to the reference module receiving the reference control signal.

7. The semiconductor integrated circuit of claim 3 , wherein the local read-write conversion module includes a local read unit configured to transmit data of at least one of the first data line or the first complementary data line to the second data line during the memory read operation and in response to the local read-write conversion module receiving the read control signal of the read write control signal, wherein the local read unit comprises at least two local transistors and a conductivity of the at least two local transistor is stronger than a conductivity of the at least one reference transistor.

8. The semiconductor integrated circuit of claim 7 , wherein a channel width of the at least one reference transistor is less than a channel width of the at least two local transistors.

9. The semiconductor integrated circuit of claim 7 , wherein the at least two local transistors include a local read control transistor and a local read transmission transistor, wherein the local read control transistor and the local read transmission transistor from a conductive pathway between the second data line and a ground to discharge the voltage potential of the second data line, wherein the local read control transistor and the local read transmission transistor from the conductive pathway in response to the local read-write conversion module receiving the reference control signal and the read control signal of the read write control signal, respectively.

10. The semiconductor integrated circuit of claim 9 , the at least one reference transistor is a reference transmission transistor that becomes conductive in response to the reference module receiving the reference control signal and causes the voltage potential of the reference signal to the amplifier module to be reduced, wherein a channel width of the reference transmission transistor is less than a channel width of the local read transmission transistor.

11. The semiconductor integrated circuit of claim 10 , wherein the channel width of the reference control transistor is less than or equal to ⅔ of the channel width of the local read control transistor, and wherein the channel width of the reference transmission transistor is less than or equal to ⅔ of the channel width of the local read transmission transistor.

12. The semiconductor integrated circuit of claim 10 , wherein the channel width of the reference control transistor is ½ of the channel width of the local read control transistor, and wherein the channel width of the reference transmission transistor is ½ of the channel width of the local read transmission transistor.

13. The semiconductor integrated circuit of claim 1 , wherein the amplifier module is a differential amplifier, wherein a first input end of the differential amplifier is coupled to the second data line and a second input end of the differential amplifier is coupled to the reference data line.

14. The semiconductor integrated circuit of claim 1 , further comprising:
a local amplifier module configured to amplify data of the first data line and data of the first complementary data line.

15. The semiconductor integrated circuit of claim 14 , wherein the local amplifier module comprises a first phase inverter and a second phase inverter, wherein an input end of the first phase inverter is coupled to the first data line and an output end of the first phase inverter is coupled to the first complementary data line, and wherein an input end of the second phase inverter is coupled to the output end of the first phase inverter and the first complementary data line, and an output end of the second phase inverter is coupled to the input end of the first phase inverter and the first data line.

16. A memory comprising:
a plurality of sense amplifier arrays;
a plurality of memory cell arrays, wherein each of the plurality of memory cells is coupled to at least one of the plurality of sense amplifier arrays to form a memory array; and
a semiconductor integrated circuit, wherein the semiconductor integrated circuit comprises:
a first data line coupled to a bit line through a column selection module, a first complementary data line coupled to a complementary bit line through the column selection module, a second data line, and a reference data line configured to provide a reference signal;
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Assignees

• Changxin Memory Tech Inc

Inventors

• Shang Weibing
• Chen Jixing
• Wu Xianjun

Classifications

• G11C11/4091 Primary

  Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating · CPC title

• G11C7/1048

  Data bus control circuits, e.g. precharging, presetting, equalising · CPC title

• G11C7/1078

  Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits · CPC title

• G11C11/4093

  Input/output [I/O] data interface arrangements, e.g. data buffers · CPC title

• G11C11/4094

  Bit-line management or control circuits · CPC title