Mechanism for integrating I/O hypervisor with a combined DPU and server solution

Patent metadata

Field	Value
Publication number	US-11847015-B2
Application number	US-202217582055-A
Country	US
Kind code	B2
Filing date	Jan 24, 2022
Priority date	Jan 24, 2022
Publication date	Dec 19, 2023
Grant date	Dec 19, 2023

Abstract

A combined data processing unit (DPU) and server solution with DPU operating system (OS) integration is described. A DPU OS is executed on a DPU or other computing device, where the DPU OS exercises secure calls provided by a DPU's trusted firmware component, that may be invoked by DPU OS components to abstract DPU vendor-specific and server vendor-specific integration details. An invocation of one of the secure calls made on the DPU to communicate with its associated server computing device is identified. In an instance in which the one of the secure calls is invoked, the secure call invoked is translated into a call or request specific to an architecture of the server computing device and the call is performed, which may include sending a signal to the server computing device in a format interpretable by the server computing device.

First claim

Therefore, the following is claimed:

1. A system for data processing unit (DPU) operating system integration in a combined server and DPU solution, comprising:
a server computing device and a data processing unit communicatively coupled to one another, and each comprising at least one hardware processor; and
program instructions stored in memory that, when executed by the at least one hardware processor of the DPU, direct DPU to:
execute a DPU operating system on the DPU, wherein the DPU operating system exercises a plurality of secure calls implemented by a DPU trusted firmware component, implemented by DPU trusted firmware to be invoked by components of the DPU operating system;
identify an invocation of one of the secure calls made on the DPU to communicate with the server computing device or perform another function associated with the DPU; and
in an instance in which the one of the secure calls is invoked, translate the one of the secure calls into a call or request specific to an architecture of the server computing device and perform the call, wherein the call being performed comprises sending a signal to the server computing device in a format interpretable by the server computing device; wherein
the DPU implements a reduced instruction set computer (RISC) architecture capable of executing the DPU operating system;
the server computing device comprises a baseboard management controller (BMC); and
the one of the secure calls made to the DPU is a secure monitor call (SMC) translated to a request to the baseboard management controller of the server computing device, the secure monitor call being a call compliant with the RISC architecture.

2. The system of claim 1 , wherein the signal sent to the server computing device is a fatal peripheral component interconnect express (PCIe) error interrupt that directs an operating system of the server computing device to notify endpoints visible to the operating system of the server computing device.

3. The system of claim 1 , wherein the signal sent to the server computing device is a power-on self-test code sent to the baseboard management controller of the server computing device.

4. The system of claim 1 , wherein the signal sent to the server computing device is a DPU operating system status signal sent to the baseboard management controller of the server computing device.

5. The system of claim 1 , wherein the signal sent to the server computing device is a DPU halt request communicated as an advanced configuration and power interface (ACPI) power button device event.

6. The system of claim 1 , wherein the signal sent to the server computing device is a DPU crash request from the baseboard management controller.

7. The system of claim 1 , wherein:
the DPU is a first computing device;
the server system further comprises a second computing device;
the one of the secure calls from the DPU operating system is translated into the call specific to the architecture of the first computing device by: identifying the architecture of the first server computing device; identifying a function to invoke based on the architecture of the first server computing device; and executing the function in response to the secure call being invoked; and
the at least one hardware processor of the DPU is further directed to identify the architecture of the second computing device; identify a function to invoke based on the architecture of the second computing device; and execute the function in response to the secure call being invoked.

8. A method for data processing unit (DPU) integration in a combined server and DPU solution, comprising:
providing a networked environment that comprises a server computing device and a DPU communicatively coupled to one another, with the server computing device containing the DPU, and the server computing and the DPU being of a different type and manufacturer;
executing a DPU operating system on the DPU, wherein the DPU operating system exercises a plurality of secure calls implemented by DPU trusted firmware to be invoked by components of the DPU operating system;
identifying an invocation of one of the secure calls made on DPU to communicate with the server computing device containing the DPU;
in an instance in which the one of the secure calls is invoked, translating the one of the secure calls into a call or request specific to the architecture of the server containing the DPU; and
executing the call, wherein the call being as executed comprises sending a signal to the server computing device in a format interpretable by the server computing device; wherein
the DPU implements a reduced instruction set computer (RISC) architecture capable of executing the DPU operating system;
the server computing device comprises a baseboard management controller (BMC); and

the one of the secure calls made to the DPU is a secure monitor call (SMC) translated to a request to the baseboard management controller of the server computing device, the secure monitor call being a call compliant with the RISC architecture.

9. The method of claim 8 , wherein the signal sent to the server computing device is a fatal peripheral component interconnect express (PCIe) error interrupt that directs an operating system of the server computing device to detect fatal errors on endpoints visible to the operating system of the server computing device due to a malfunction of the one of the DPUs or the DPU operating system of the one of the DPUs.

10. The method of claim 8 , wherein the signal sent to the server computing device is a power-on self-test code or DPU operating system service status sent to the baseboard management controller of the server computing device.

11. The method of claim 8 , wherein the signal sent to the server computing device is a DPU halt request communicated as an advanced configuration and power interface (ACPI) power button device event.

12. The method of claim 8 , wherein the signal sent to the server computing device to the DPU is a baseboard management controller-requested crash request.

13. The method of claim 8 , wherein:
the one of the DPUs is a first computing device;
the server system further comprises a second computing device;
the one of the secure calls from the DPU operating system is translated into the call specific to the architecture of the first computing device by: identifying the architecture of the first server computing device; identifying a function to invoke based on the architecture of the first server computing device; and executing the function in response to the secure call being invoked; and
the at least one hardware processor of the DPU is further directed to identify the architecture of the second computing device; identify a function to invoke based on the architecture of the second computing device; and execute the function in response to the secure call being invoked.

14. A non-transitory computer-readable medium having program instructions stored thereon executable by a data processing unit (DPU) having at least one hardware processor that, when executed by the at least one hardware processor, direct the DPU to:
execute a DPU operating system on the network interface card, wherein the DPU operating system exercises a plurality of secure calls implemented by DPU trusted firmware to be invoked by processes of the DPU operating system;
identify an invocation of one of the secure calls made on the DPU to communicate with the server computing device; and
in an instance in which the one of the secure calls is invoked, translate the one of the secure calls into a call or request specific to an architecture of the server computing devic

Assignees

• Vmware Inc

Inventors

• Warkentin Andrei
• Kotian Sunil
• Mcneill Jared
• Laplace Cyprien
• Hiriyuru Shruthi

Classifications

• G06F11/0772 Primary

  Means for error signaling, e.g. using interrupts, exception flags, dedicated error registers · CPC title

• G06F11/0778

  Dumping, i.e. gathering error/state information after a fault for later diagnosis · CPC title

• G06F11/0793

  Remedial or corrective actions (recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40) · CPC title

• G06F11/2284

  by power-on test, e.g. power-on self test [POST] · CPC title

• G06F11/24

  Marginal checking {or other specified testing methods not covered by G06F11/26, e.g. race tests} · CPC title