Technologies for providing efficient detection of idle poll loops

Patent metadata

Field	Value
Publication number	US-11847008-B2
Application number	US-201815951391-A
Country	US
Kind code	B2
Filing date	Apr 12, 2018
Priority date	Apr 12, 2018
Publication date	Dec 19, 2023
Grant date	Dec 19, 2023

Abstract

Technologies for providing efficient detection of idle poll loops include a compute device. The compute device has a compute engine that includes a plurality of cores and a memory. The compute engine is to determine a ratio of unsuccessful operations to successful operations over a predefined time period of a core of the plurality cores that is assigned to continually poll, within the predefined time period, a memory address for a change in status and determine whether the determined ratio satisfies a reference ratio of unsuccessful operations to successful operations. The reference ratio is indicative of a change in the operation of the assigned core. The compute engine is further to selectively increase or decrease a power usage of the assigned core as a function of whether the determined ratio satisfies the reference ratio. Other embodiments are also described and claimed.

First claim

The invention claimed is:

1. An apparatus comprising:
circuitry, wherein during operation of a device, the circuitry is to:
access data indicative of branch hits associated with operation of the device;
access data indicative of branch misses associated with operation of the device; and
set a level of power supplied to the device and a frequency of operation of the device based on the branch hits and branch misses associated with operation of the device.

2. The apparatus of claim 1 , wherein the operation of the device comprises packet processing.

3. The apparatus of claim 1 , wherein the operation of the device comprises execution of a virtual machine (VM) to perform packet processing.

4. The apparatus of claim 1 , wherein the branch hits and branch misses are associated with branch prediction operations.

5. The apparatus of claim 1 , wherein the set the level of power supplied to the device and a frequency of operation of the device is based on a ratio of branch misses to branch hits.

6. The apparatus of claim 1 , comprising the device, wherein the device comprises one or more of: a core, a processor, or field-programmable gate array (FPGA).

7. The apparatus of claim 1 , comprising:
a memory and
a network interface, wherein the network interface is to store packets into the memory and wherein the branch hits and branch misses associated with operation of the device are associated with attempts to process the packets.

8. The apparatus of claim 1 , wherein the circuitry comprises a performance monitor unit (PMU).

9. One or more non-transitory machine-readable storage media comprising a plurality of instructions stored thereon that, in response to being executed, cause circuitry to:
during operation of a device:
access data indicative of branch hits associated with operation of the device;
access data indicative of branch misses associated with operation of the device; and
set a level of power supplied to the device and a frequency of operation of the device based on the branch hits and branch misses associated with operation of the device.

10. The one or more non-transitory machine-readable storage media of claim 9 , wherein the operation of the device comprises packet processing.

11. The one or more non-transitory machine-readable storage media of claim 9 , wherein the operation of the device comprises execution of a virtual machine (VM) to perform packet processing.

12. The one or more non-transitory machine-readable storage media of claim 9 , wherein the branch hits and branch misses are associated with branch prediction operations.

13. The one or more non-transitory machine-readable storage media of claim 9 , wherein the set the level of power supplied to the device and a frequency of operation of the device is based on a ratio of branch misses to branch hits.

14. The one or more non-transitory machine-readable storage media of claim 9 , wherein the device comprises one or more of: a core, a processor, or field-programmable gate array (FPGA).

15. The one or more non-transitory machine-readable storage media of claim 9 , wherein a network interface is to store packets into memory and wherein the branch hits and branch misses associated with operation of the device are associated with attempts to process the packets.

16. A method comprising:
during operation of a device:
accessing data indicative of branch hits associated with operation of the device;
accessing data indicative of branch misses associated with operation of the device; and
setting a level of power supplied to the device and a frequency of operation of the device based on the branch hits and branch misses associated with operation of the device.

17. The method of claim 16 , wherein the operation of the device comprises packet processing.

18. The method of claim 16 , wherein the operation of the device comprises execution of a virtual machine (VM) to perform packet processing.

19. The method of claim 16 , wherein the branch hits and branch misses are associated with branch prediction operations.

20. The method of claim 16 , wherein the set the level of power supplied to the device and a frequency of operation of the device is based on a ratio of branch misses to branch hits.

21. The method of claim 16 , wherein the device comprises one or more of: a core, a processor, or field-programmable gate array (FPGA).

22. The method of claim 16 , wherein a network interface is to store packets into memory and wherein the branch hits and branch misses associated with operation of the device are associated with attempts to process the packets.

Assignees

• Intel Corp

Inventors

• Hunt David
• Power Niall
• Devey Kevin
• Wei Changzheng
• Richardson Bruce
• Tamir Eliezer
• Cunningham Andrew
• Macnamara Chris
• Marjanovic Nemanja
• Sexton Rory
• Browne John

Classifications

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title

• G06F1/3228 Primary

  Monitoring task completion, e.g. by use of idle timers, stop commands or wait commands · CPC title

• G06F1/324

  by lowering clock frequency · CPC title

• G06F1/3296

  by lowering the supply or operating voltage · CPC title

• G06F15/00

  Digital computers in general (details G06F1/00 – G06F13/00); Data processing equipment in general · CPC title