Charge storage apparatus and methods
US-2020303391-A1 · Sep 24, 2020 · US
US11844220B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-11844220-B2 |
| Application number | US-202218074055-A |
| Country | US |
| Kind code | B2 |
| Filing date | Dec 2, 2022 |
| Priority date | May 13, 2020 |
| Publication date | Dec 12, 2023 |
| Grant date | Dec 12, 2023 |
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
What the patent document calls the invention.
A short plain-language summary of the technical disclosure.
Who owns or filed the patent and who is credited as inventor.
Filing, priority, publication, and grant dates set the timeline.
The legal scope of protection — read this for what is actually claimed.
Technology tags used to group this patent with similar filings.
Prior art links and similar publications in this corpus.
Official abstract text for this publication.
Some embodiments include an integrated assembly having a first structure containing semiconductor material, and having a second structure contacting the first structure. The first structure has a composition along an interface with the second structure. The composition includes additive to a concentration within a range of from about 10 18 atoms/cm 3 to about 10 21 atoms/cm 3 . The additive includes one or more of carbon, oxygen, nitrogen and sulfur. Some embodiments include methods of forming integrated assemblies.
Opening claim text (preview).
We claim: 1. A method of forming an integrated assembly, comprising: forming a source structure comprising semiconductor material over metal-containing material; additive being within a region of the semiconductor material to a concentration within a range of from 10 18 atoms/cm 3 to 10 21 atoms/cm 3 ; the additive comprising one or more of the group of carbon, oxygen, nitrogen and sulfur; etching into the region of the semiconductor material utilizing an etchant comprising phosphoric acid; the etching forming an opening which extends into, but not entirely through, the semiconductor material of said region; and forming a second structure over the source structure and extending into said opening. 2. The method of claim 1 wherein the additive includes the carbon. 3. The method of claim 1 wherein the additive includes the nitrogen. 4. The method of claim 1 wherein the additive includes the oxygen. 5. The method of claim 1 wherein the additive includes the sulfur. 6. The method of claim 1 wherein the second structure comprises insulative material. 7. The method of claim 1 wherein the semiconductor material comprises n-type silicon having n-type dopant therein to a concentration of at least 10 20 atoms/cm 3 . 8. The method of claim 1 wherein the semiconductor material comprises p-type silicon having p-type dopant therein to a concentration of at least 10 20 atoms/cm 3 . 9. A method of forming an integrated assembly, comprising: forming a stack of alternating first and second levels over a source structure; the first levels comprising sacrificial material and the second levels comprising a first insulative material; the source structure comprising semiconductor material over metal-containing material; forming a trench which extends through the stack and to a region of the semiconductor material; providing carbon within the region of the semiconductor material; removing the sacrificial material of the first levels to leave voids; forming conductive material within the voids; and after forming the conductive material, forming a panel within the trench; the panel comprising a second insulative material. 10. The method of claim 9 wherein the carbon is provided to a concentration within a range of from 10 18 atoms/cm 3 to 10 21 atoms/cm 3 . 11. The method of claim 9 wherein the carbon is provided within the region prior to forming the trench. 12. The method of claim 9 wherein the panel consists essentially of the second insulative material. 13. The method of claim 9 wherein the panel separates a first block region of a memory arrangement from a second block region of the memory arrangement. 14. The method of claim 13 wherein the first and second block regions include memory cells, with the individual memory cells including charge-trapping material adjacent channel material; and wherein the channel material is electrically coupled with the source structure.
Anisotropic liquid etching (H10P50/61 takes precedence) · CPC title
of conductive or resistive materials · CPC title
by chemical means · CPC title
the channels comprising vertical portions, e.g. U-shaped channels · CPC title
Electricity · mapped topic
Related publications grouped by family.
Answers are generated from the same data shown on this page.