Fractal calculating device and method, integrated circuit and board card

Patent metadata

Field	Value
Publication number	US-11841822-B2
Application number	US-202117560490-A
Country	US
Kind code	B2
Filing date	Dec 23, 2021
Priority date	Apr 27, 2019
Publication date	Dec 12, 2023
Grant date	Dec 12, 2023

Abstract

A fractal computing device according to an embodiment of the present application may be included in an integrated circuit device. The integrated circuit device includes a universal interconnect interface and other processing devices. The calculating device interacts with other processing devices to jointly complete a user specified calculation operation. The integrated circuit device may also include a storage device. The storage device is respectively connected with the calculating device and other processing devices and is used for data storage of the computing device and other processing devices.

First claim

What is claimed is:

1. A fractal calculating device, comprising a plurality of layers of calculation units, wherein each layer of calculation units includes:
a serial decomposing unit configured to receive an upper layer of fractal instruction from an upper layer of calculation units and decompose the upper layer of fractal instruction into a plurality of serial sub-instructions;
an instruction decoding unit configured to decode the plurality of serial sub-instructions into local fractal instructions according to hardware resources of the calculation units; and
an operation execution unit configured to issue the local fractal instructions to a lower layer of calculation units to generate a calculation result,
wherein the serial decomposition unit includes:
an instruction queue configured to temporarily store the upper layer of fractal instruction;
a serial decomposer configured to obtain the upper layer of fractal instruction from the instruction queue and decompose the fractal instruction into a plurality of serial sub-instructions; and
a sub-instruction queue configured to temporarily store the plurality of serial sub-instructions,
wherein the instruction decoding unit includes:
a down-layer decoder configured to sequentially obtain a plurality of serial sub-instructions from the sub-instruction queue to generate a lower layer of instructions; and
a parallel decomposer configured to decompose the lower layer of instructions into local fractal instructions in parallel.

2. The fractal calculating device of claim 1 , wherein the operation execution unit includes a plurality of fractal functional units configured to execute an issued task.

3. The fractal calculating device of claim 2 , wherein each layer of calculation units also include a local memory, and the hardware resources include one of the capacity limitation of the local memory, the ability of the serial decomposer to decompose the upper layer of fractal instructions, the calculation ability of the lower layer of calculation units, and the number of the fractal functional units.

4. The fractal calculating device of claim 3 , wherein each layer of calculation units also include a data loading unit which includes a DMA (direct memory access) controller; the down-layer decoder generates a direct memory access instruction pointing to the local memory; and the DMA exchanges data between the local memory and an upper layer of memory according to the direct memory access instruction.

5. The fractal calculating device of claim 4 , wherein the data loading unit includes a DMA configured to send the data stored in the local memory to the plurality of fractal functional units to execute the issued task.

6. The fractal calculating device of claim 1 , wherein the instruction decoding unit includes a reduction controller configured to decode the lower layer of instructions into local reduction instructions; each layer of calculation units also include an operation reduction unit which includes a local functional unit, where the operation reduction unit is configured to reduce the calculation result according to the local reduction instructions.

7. An integrated circuit device comprising the fractal calculating device of claim 1 .

8. A board card comprising the integrated circuit device of claim 7 .

9. A fractal calculating method, comprising:
in response to an upper layer of fractal instruction from an upper layer of calculation units, decomposing the upper layer of fractal instruction into a plurality of serial sub-instructions;
decoding the plurality of serial sub-instructions into local fractal instructions according to hardware resources of the calculation units; and
issuing the local fractal instructions to a lower layer of calculation units to generate a calculation result,
wherein the decomposing the upper layer of fractal instruction into the plurality of serial sub-instructions includes:
temporarily storing the upper layer of fractal instruction;
obtaining the upper layer of fractal instruction from the instruction queue and decompose the fractal instruction into a plurality of serial sub-instructions; and
temporarily storing the plurality of serial sub-instructions,
wherein decoding the plurality of serial sub-instructions into local fractal instructions according to hardware resources of the calculation units includes:
sequentially obtaining a plurality of serial sub-instructions from the sub-instruction queue to generate a lower layer of instructions; and
decomposing the lower layer of instructions into local fractal instructions in parallel.

10. The fractal calculating method of claim 9 , wherein the hardware resources include one of the capacity limitation of the local memory, the ability to decompose the upper layer of fractal instruction, and the calculation ability of the lower layer of calculation units.

Assignees

• Cambricon Tech Corp Ltd

Inventors

• Liu Shaoli
• Jiang Guang
• Zhao Yongwei
• Liang Jun

Classifications

• G06F15/76 Primary

  Architectures of general purpose stored program computers (with program plugboard G06F15/08; multicomputers G06F15/16) · CPC title

• G06F9/3818

  Decoding for concurrent execution · CPC title

• G06F9/3836

  Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution · CPC title

• G06F17/16 Primary

  Matrix or vector computation {, e.g. matrix-matrix or matrix-vector multiplication, matrix factorization (matrix transposition G06F7/78)} · CPC title

• G06N3/063

  using electronic means · CPC title