Display panel

US11839121B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11839121-B2
Application numberUS-202117209833-A
CountryUS
Kind codeB2
Filing dateMar 23, 2021
Priority dateNov 2, 2018
Publication dateDec 5, 2023
Grant dateDec 5, 2023

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  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A display panel including a substrate including a display area surrounding an opening area and a non-display area between the opening area and the display area; a plurality of display elements on the display area; a plurality of scan lines extending in a first direction and detouring around an edge of the opening area; a plurality of data lines extending in a second direction that intersects with the first direction, the plurality of data lines detouring around the edge of the opening area; and a plurality of emission control lines extending in the first direction and detouring around the edge of the opening area.

First claim

Opening claim text (preview).

What is claimed is: 1. A display panel, comprising: a substrate including a display area surrounding an opening area and a non-display area between the opening area and the display area; a plurality of display elements in the display area; a plurality of scan lines extending in a first direction in the display area and detouring around the opening area in the non-display area; a plurality of data lines extending in a second direction crossing the first direction in the display area, the plurality of data lines detouring around the opening area in the non-display area; a plurality of voltage lines extending in the second direction in the display area; and a plurality of electrode voltage lines extending in the first direction in the display area and electrically connected to the plurality of voltage lines, wherein the plurality of voltage lines and the plurality of electrode voltage lines form a mesh structures in a plan view. 2. The display panel as claimed in claim 1 , further comprising: a plurality of circuits electrically coupled to the plurality of display elements, respectively, wherein each of the plurality of circuits includes transistors and a capacitor, wherein the capacitor comprises a first capacitor electrode and a second capacitor electrode that is electrically connected the plurality of electrode voltage lines. 3. The display panel as claimed in claim 2 , wherein a portion of each of the plurality of electrode voltage lines includes the second capacitor electrode of the capacitor. 4. The display panel as claimed in claim 1 , wherein the plurality of electrode voltage lines comprises a first electrode voltage line including a first part and a second part that are spaced each other with the opening area therebetween. 5. The display panel as claimed in claim 1 , further comprising: a first insulation layer between the plurality of scan lines and the plurality of electrode voltage lines. 6. The display panel as claimed in claim 5 , further comprising: a second insulation layer between the plurality of electrode voltage lines and the plurality of data lines, wherein the second insulation layer is over the first insulation layer. 7. A display panel, comprising: a substrate having a hole, the substrate including a display area surrounding the hole and a non-display area between the hole and the display area; a plurality of display elements in the display area; a plurality of scan lines extending in a first direction in the display area and detouring around the hole in the non-display area; a plurality of data lines extending in a second direction crossing the first direction in the display area, the plurality of data lines detouring around the hole in the non-display area; a plurality of voltage lines extending in the second direction in the display area; and a plurality of electrode voltage lines extending in the first direction in the display area and electrically connected to the plurality of voltage lines, wherein the plurality of voltage lines and the plurality of electrode voltage lines form a mesh structures in a plan view. 8. The display panel as claimed in claim 7 , further comprising: a plurality of circuits electrically coupled to the plurality of display elements, respectively, wherein each of the plurality of circuits includes transistors and a capacitor, wherein the capacitor comprises a first capacitor electrode and a second capacitor electrode that is electrically connected the plurality of electrode voltage lines. 9. The display panel as claimed in claim 8 , wherein a portion of each of the plurality of electrode voltage lines includes the second capacitor electrode of the capacitor. 10. The display panel as claimed in claim 7 , wherein the plurality of electrode voltage lines comprises a first electrode voltage line including a first part and a second part that are spaced each other, wherein the hole of the substrate is between the first part and the second part of the first electrode voltage line in a plan view. 11. The display panel as claimed in claim 7 , further comprising: a first insulation layer between the plurality of scan lines and the plurality of electrode voltage lines; and a second insulation layer over the first insulation layer, wherein the plurality of electrode voltage lines are under the second insulation layer and the plurality of data lines are over the second insulation layer. 12. A display device, comprising: a display panel including a hole area and a display area surrounding the hole area; and a component located in the hole area of the display panel, wherein the display panel comprises: a substrate having a hole corresponding to the hole area of the display panel; a plurality of light emitting diodes on the substrate, the plurality of light emitting diodes being arranged in the display area; a plurality of circuits electrically coupled to the plurality of light emitting diodes, respectively, wherein each of the plurality of circuits includes transistors and a capacitor; a plurality of scan lines electrically coupled to the plurality of circuits, the plurality of scan lines extending in a first direction in the display area and detouring along an edge of the hole of the substrate in an area between the hole area and the display area; a plurality of data lines extending in a second direction crossing the first direction in the display area, and detouring along an edge of the hole of the substrate in the area between the hole area and the display area; a plurality of voltage lines extending in the second direction in the display area; and a plurality of electrode voltage lines extending in the first direction in the display area and electrically connected to the plurality of voltage lines, wherein the plurality of voltage lines and the plurality of electrode voltage lines form a mesh structures in a plan view. 13. The display device as claimed in claim 12 , wherein the capacitor comprises a first capacitor electrode and a second capacitor electrode that is electrically connected the plurality of electrode voltage lines. 14. The display device as claimed in claim 13 , wherein a portion of each of the plurality of electrode voltage lines includes the second capacitor electrode of the capacitor. 15. The display device as claimed in claim 12 , wherein the plurality of electrode voltage lines comprises a first electrode voltage line including a first part and a second part that are spaced each other with the hole of the substrate therebetween. 16. The display device as claimed in claim 1 , wherein the display panel further comprises: a first insulation layer between the plurality of scan lines and the plurality of electrode voltage lines; and a second insulation layer over the first insulation layer, wherein the plurality of electrode voltage lines are under the second insulation layer and the plurality of data lines are over the second insulation layer. 17. The display device as claimed in claim 1 , wherein the component comprises an electronic element that uses light or sounds. 18. The display device as claimed in claim 17 , wherein the electronic element uses at least one selected from a visible light, an infrared light, and ultraviolet light. 19. The display device as claimed in claim 17 , wherein the electronic element comprises at least one selected from a camera, a distance sensor, a fingerprint sensor, a small lamp, and a speaker. 20. The display device as claimed in claim 17 , wherein the display device comprises a mo

Assignees

Inventors

Classifications

  • The addressing of the pixel, in a display other than an active matrix LCD, involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependent on signals of two data electrodes · CPC title

  • with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes · CPC title

  • forming a memory circuit, e.g. a dynamic memory with one capacitor · CPC title

  • used for counteracting undesired variations, e.g. feedback or autozeroing · CPC title

  • Improved aperture ratio, e.g. by size reduction of the pixel circuit, e.g. for improving the pixel density or the maximum displayable luminance or brightness · CPC title

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What does patent US11839121B2 cover?
A display panel including a substrate including a display area surrounding an opening area and a non-display area between the opening area and the display area; a plurality of display elements on the display area; a plurality of scan lines extending in a first direction and detouring around an edge of the opening area; a plurality of data lines extending in a second direction that intersects wi…
Who is the assignee on this patent?
Samsung Display Co Ltd
What technology area does this patent fall under?
Primary CPC classification G09G3/3233. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Dec 05 2023 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 7 related publications on this page (citations in our corpus or others sharing the same primary CPC).