Method for manufacturing optoelectric semiconductor component and optoelectric semiconductor component device

Patent metadata

Field	Value
Publication number	US-11837844-B2
Application number	US-201816961901-A
Country	US
Kind code	B2
Filing date	Dec 27, 2018
Priority date	Jan 15, 2018
Publication date	Dec 5, 2023
Grant date	Dec 5, 2023

Abstract

A method for singulating semiconductor components ( 20 ) is specified, said method comprising the steps of providing a carrier ( 21 ), applying at least two semiconductor chips ( 22 ) on the carrier ( 21 ), etching at least one break nucleus ( 23 ) at a side of the carrier ( 21 ) facing the semiconductor chips ( 22 ), and singulating at least two semiconductor components ( 20 ) by breaking the carrier ( 21 ) along the at least one break nucleus ( 23 ). The at least one break nucleus ( 23 ) extends at least in places in a vertical direction (z), the vertical direction (z) being perpendicular to a main extension plane of the carrier ( 21 ), and the at least one break nucleus ( 23 ) is arranged between the two semiconductor chips ( 22 ) in a lateral direction (x), the lateral direction (x) being parallel to the main extension plane of the carrier ( 21 ). Further, each of the semiconductor components ( 20 ) comprises at least one of the semiconductor chips ( 22 ), and the expansion of the at least one break nucleus ( 23 ) in the vertical direction (z) is at least 1 % of the expansion of the carrier ( 21 ) in the vertical direction (z). Furthermore, a semiconductor component ( 20 ) is specified.

First claim

The invention claimed is:

1. A method for singulating semiconductor components, the method comprising:
providing a carrier;
applying at least two semiconductor chips on the carrier;
etching at least one break nucleus at a side of the carrier facing the semiconductor chips;
applying a passivation layer only on at least one portion of at least one break nucleus and not on an other portion of the break nucleus; and
singulating at least two semiconductor components by breaking the carrier along the at least one break nucleus, wherein
the at least one break nucleus extends at least in places in a vertical direction (z), the vertical direction (z) being perpendicular to a main extension plane of the carrier,
the at least one break nucleus is arranged between the two semiconductor chips in a lateral direction (x), the lateral direction (x) being parallel to the main extension plane of the carrier,
each of the semiconductor components comprises at least one of the semiconductor chips, and
the expansion of the at least one break nucleus in the vertical direction (z) is at least 1% of the expansion of the carrier in the vertical direction (z).

2. The method according to claim 1 , wherein:
break edges are produced by the singulating, and
at least one of the break edges has a notch at least in places,
the break edge shows traces of the etching in the area of the notch.

3. The method according to claim 2 , wherein the expansion of the at least one break nucleus or notch in the vertical direction (z) is at least 5% and at most 40% of the expansion of the carrier in the vertical direction (z).

4. The method according to claim 2 , wherein the expansion of the break nucleus or notch in a lateral direction (x) is smaller than the expansion of one of the at least two semiconductor chips in the lateral direction (x).

5. The method according to claim 2 , wherein the expansion of the break nucleus or notch in a lateral direction (x) is greater than the expansion of one of the at least two semiconductor chips in the lateral direction (x).

6. The method according to claim 2 , wherein in a plane parallel to the main extension plane of the carrier, a main extension direction of the break nucleus or the notch is perpendicular to a crystal direction of the carrier.

7. The method according to claim 2 , wherein the expansion of the break nucleus or notch is not constant in the vertical direction (z).

8. The method according to claim 2 , wherein a passivation layer is applied at least in places on the break nucleus.

9. The method according to claim 1 , wherein the break nucleus is generated by plasma etching.

10. The method according to claim 1 , wherein the semiconductor components are semiconductor lasers.

11. The method according to claim 1 , wherein prior to breaking the carrier along the at least one break nucleus, the carrier is broken along a crystal direction.

12. The method according to claim 1 , wherein a shape of the break nucleus is asymmetrical or wherein the break nucleus has a shape of a trench having two opposite side walls of different shapes.

13. The method of claim 1 , wherein the areas of the break nucleus which are not covered by the passivation layer are roughened.

14. A semiconductor component comprising:
a component carrier; and
a semiconductor chip which is arranged on the component carrier, wherein
the component carrier has break edges which extend transversely to a main extension plane of the component carrier,
at least one of the break edges has a notch at least in places, so that a lateral expansion of the semiconductor component in a lateral direction (x) on a top side of the semiconductor component facing away from the component carrier is smaller at least in places than a lateral expansion of the semiconductor component in the lateral direction (x) in the area of the component carrier, the lateral direction (x) being parallel to the main extension plane of the component carrier,
the break edge shows only in places traces of an etching process in an area of the notch, and
the expansion of the notch in the vertical direction (z) is at least 1% of the expansion of the component carrier in the vertical direction (z), the vertical direction (z) being perpendicular to the main extension plane of the component carrier,
wherein the notch comprises in some areas that have a higher surface roughness than other areas as a result of a chemically roughing process.

15. The semiconductor component according to claim 14 , wherein the expansion of the at least one notch in the vertical direction (z) is at least 5% and at most 40% of the expansion of the component carrier in the vertical direction (z).

16. The semiconductor component according to claim 14 , wherein the semiconductor components are semiconductor lasers.

17. The semiconductor component according to claim 14 , wherein the expansion of the notch in a lateral direction (x) is smaller than the expansion of a semiconductor chip in the lateral direction (x).

18. The semiconductor component according to claim 14 , wherein the expansion of the notch in a lateral direction (x) is greater than the expansion of a semiconductor chip in the lateral direction (x).

19. A method for singulating semiconductor components, comprising:
providing a carrier;
applying at least two semiconductor chips on the carrier;
etching at least one break nucleus at a side of the carrier facing the semiconductor chips;
applying a passivation layer only on at least one portion of at least one break nucleus and not on an other portion of the break nucleus; and
singulating at least two semiconductor components by breaking the carrier along the at least one break nucleus, wherein
the at least one break nucleus extends at least in places in a vertical direction (z), the vertical direction (z) being perpendicular to a main extension plane of the carrier,
the at least one break nucleus is arranged between the two semiconductor chips in a lateral direction (x), the lateral direction (x) being parallel to the main extension plane of the carrier,
each of the semiconductor components comprises at least one of the semiconductor chips, and
the expansion of the at least one break nucleus in the vertical direction (z) is at least 1% of the expansion of the carrier in the vertical direction (z), and
the break nucleus has at least two bottom surfaces which are located in different vertical positions.

20. The method of claim 19 , wherein the bottom surfaces of the break nucleus are parallel to the main extension plane of the carrier.

Assignees

• Osram Oled Gmbh

Inventors

• Brückner John
• Heine Urs
• Gerhard Sven
• Nähle Lars
• Löffler Andreas
• Somers André

Classifications

• H10P52/00

  Grinding, lapping or polishing of wafers, substrates or parts of devices · CPC title

• H10P50/00

  Etching of wafers, substrates or parts of devices · CPC title

• H10P54/00

  Cutting or separating of wafers, substrates or parts of devices · CPC title

• H10H20/01 Primary

  Manufacture or treatment · CPC title

• H01S5/0203 Primary

  Etching · CPC title