Ceramic electronic device and manufacturing method of ceramic electronic device

Patent metadata

Field	Value
Publication number	US-11837409-B2
Application number	US-202217590059-A
Country	US
Kind code	B2
Filing date	Feb 1, 2022
Priority date	Mar 26, 2021
Publication date	Dec 5, 2023
Grant date	Dec 5, 2023

Abstract

A ceramic electronic device includes a plurality of dielectric layers of which a main component is a ceramic having a perovskite structure, and a plurality of internal electrode layers, each of which is stacked through each of the plurality of dielectric layers and includes a co-material which is inactive against the main component of the plurality of dielectric layers.

First claim

What is claimed is:

1. A ceramic electronic device comprising:
a plurality of dielectric layers of which a main component is a ceramic having a perovskite structure; and
a plurality of internal electrode layers, each of which is alternatively stacked with each of the plurality of dielectric layers and includes metal crystal grains, and a co-material which is inactive against the main component of the plurality of dielectric layers, without including a ceramic having a same composition as the ceramic of the main component of the plurality of dielectric layers.

2. The ceramic electronic device as claimed in claim 1 , wherein the co-material is an amorphous silica grain.

3. The ceramic electronic device as claimed in claim 1 , wherein the co-material is enclosed in each of the plurality of internal electrode layers.

4. The ceramic electronic device as claimed in claim 1 , wherein a thickness of each of the dielectric layers is 2.0 μm or less.

5. The ceramic electronic device as claimed in claim 1 , wherein an average grain diameter of the co-material is 30 nm or less in each of the plurality of internal electrode layers.

6. The ceramic electronic device as claimed in claim 1 , wherein a ratio of the co-material is 0.2 mass % or more and 10.0 mass % or less in each of plurality of internal electrode layers.

7. The ceramic electronic device as claimed in claim 1 , wherein a thickness of each of the plurality of internal electrode layers is 0.3 μm or more and 3.0 μm or less.

8. The ceramic electronic device as claimed in claim 1 , wherein an average grain diameter of the metal crystal grains is 30 nm or more and 250 nm or less in each of the plurality of internal electrode layers.

9. A manufacturing method of a ceramic electronic device comprising:
forming a multilayer structure by stacking a plurality of stack units, each of which has a structure in which a pattern of metal conductive paste including a co-material is printed on a dielectric green sheet of a dielectric material including ceramic material powder having a perovskite structure, the pattern of metal conductive paste including metal powder and the co-material without including ceramic material powder having a same composition as the ceramic material powder included in the dielectric material; and
firing the multilayer structure,
wherein the co-material does not react with the ceramic material powder at a temperature of the firing of the multilayer structure.

10. The method as claimed in claim 9 , wherein the co-material is an amorphous silica grain.

11. The method as claimed in claim 9 , wherein a thickness of the dielectric green sheet is adjusted so that a thickness of a dielectric layer made by firing the dielectric green sheet becomes 2.0 μm or less.

12. The method as claimed in claim 9 , wherein an average particle diameter of the co-material is 30 nm or less.

13. The method as claimed in claim 9 , wherein a ratio of the co-material is 0.2 mass % or more and 10.0 mass % or less in the metal conductive paste.

14. The method as claimed in claim 9 , wherein a thickness of the metal conductive paste is adjusted so that a thickness of an internal electrode layer made by firing the metal conductive paste becomes 0.3 μm or more and 3.0 μm or less.

15. The method as claimed in claim 9 , wherein an average particle diameter of metal powder of the metal conductive paste is 30 nm or more and 250 nm or less.

Assignees

• Taiyo Yuden Kk

Inventors

• Morita Koichiro

Classifications

• H01G4/1227 Primary

  based on alkaline earth titanates · CPC title

• C04B35/06

  based on oxide mixtures derived from dolomite · CPC title

• C04B35/4682

  based on BaTiO3 perovskite phase · CPC title

• H01G4/008

  Selection of materials · CPC title

• H01G4/012

  Form of non-self-supporting electrodes · CPC title