Substrate, printing apparatus, and manufacturing method

Patent metadata

Field	Value
Publication number	US-11837301-B2
Application number	US-202217685479-A
Country	US
Kind code	B2
Filing date	Mar 3, 2022
Priority date	Mar 10, 2021
Publication date	Dec 5, 2023
Grant date	Dec 5, 2023

Abstract

A substrate includes a plurality of memory units each including an anti-fuse element and a switching element configured to switch application of a predetermined voltage to the anti-fuse element, a wiring to which the plurality of memory units are connected, a first electrode pad to which a voltage for supplying the predetermined voltage to the wiring is applied, and a second electrode pad to which a voltage for supplying the predetermined voltage to the wiring is applied.

First claim

What is claimed is:

1. A substrate comprising:
a plurality of memory units each including an anti-fuse element and a switching element configured to switch application of a predetermined voltage to the anti-fuse element;
a first wiring and a second wiring between which the plurality of memory units are connected in parallel, the second wiring being set at a ground potential;
a first electrode pad to which a voltage for supplying the predetermined voltage to the first wiring is applied; and
a second electrode pad to which a voltage for supplying the predetermined voltage to the first wiring is applied.

2. The substrate according to claim 1 , further comprising a voltage applying unit connected between the first electrode pad and the first wiring and configured to apply the predetermined voltage to the wiring based on the voltage applied to the first electrode pad.

3. The substrate according to claim 1 , wherein the second electrode pad is connected to the first wiring.

4. The substrate according to claim 1 , wherein the first electrode pad is an electrode pad to which an internal power supply of a device including the substrate is connected, and
wherein the second electrode pad is an electrode pad to which an external power supply outside the device is connected.

5. The substrate according to claim 1 , wherein the memory unit includes a resistive element connected between the anti-fuse element and the first wiring.

6. The substrate according to claim 1 , wherein the memory unit includes a resistive element connected in parallel with the anti-fuse element.

7. The substrate according to claim 1 , wherein the anti fuse element has a MOS structure,
wherein, when the predetermined voltage is applied, a gate insulating film of the MOS structure causes dielectric breakdown, and a resistance value of the anti-fuse element lowers, and
wherein the switching element is a DMOS transistor.

8. The substrate according to claim 1 , further comprising a plurality of discharge elements each configured to discharge a liquid in accordance with supply of power.

9. The substrate according to claim 8 , wherein the plurality of discharge elements is a heater.

10. A printing apparatus comprising:
a printhead configured to discharge ink to a print medium; and
a power supply,
wherein the printhead comprises a substrate including a plurality of discharge elements each configured to discharge the ink, and
wherein the substrate comprises:
a plurality of memory units each including an anti fuse element and a switching element configured to switch application of a predetermined voltage to the anti-fuse element;
a first wiring and a second wiring between which the plurality of memory units are connected in parallel, the second wiring being set at a ground potential;
a first electrode pad to which a voltage for supplying the predetermined voltage to the wiring is applied by the power supply; and
a second electrode pad to which a voltage for supplying the predetermined voltage to the first wiring is applied by a power supply outside the printing apparatus.

11. A method of manufacturing a substrate,
wherein the substrate comprises:
a plurality of memory units each including an anti fuse element and a switching element configured to switch application of a predetermined voltage to the anti-fuse element; and
a first wiring and a second wiring between which the plurality of memory units are connected in parallel, the second wiring being set at a ground potential, and

wherein the method comprises:
applying the predetermined voltage to the first wiring by a first power supply and a second power supply; and
applying the predetermined voltage to the anti fuse elements of a plurality of memory units of the plurality of memory units by the corresponding switching elements.

Assignees

• Canon Kk

Inventors

• Fukuda Masashi
• Negishi Toshio
• Soeda Yasuhiro

Classifications

• G11C17/165 Primary

  Memory cells which are electrically programmed to cause a change in resistance, e.g. to permit multiple resistance steps to be programmed rather than conduct to or from non-conduct change of fuses and antifuses (digital stores using resistance random access memory elements G11C13/0002) · CPC title

• G11C5/14

  Power supply arrangements {, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels} · CPC title

• G11C7/1096

  Write circuits, e.g. I/O line write drivers · CPC title

• H10B20/20 Primary

  Programmable ROM [PROM] devices comprising field-effect components (H10B20/10 takes precedence) · CPC title

• G11C17/16 Primary

  using electrically-fusible links · CPC title