Compact low-leakage multi-bit compare CAM cell

Patent metadata

Field	Value
Publication number	US-11837289-B2
Application number	US-202117462432-A
Country	US
Kind code	B2
Filing date	Aug 31, 2021
Priority date	Aug 31, 2021
Publication date	Dec 5, 2023
Grant date	Dec 5, 2023

Abstract

A compact, low-leakage multi-bit content-addressable memory (CAM) cell is provided. The CAM devices includes a transmission gate, having a positive field effect transistor (“PFET”) and a negative field effect transistor (“NFET”), configured to compare a compare data input with storage node data having a first logic state. The CAM devices includes a passgate, in communication with the transmission gate, configured to compare the compare data input having a first logic state with the storage node data having a second logic state, wherein the passgate is an n-channel metal oxide semiconductor (NMOS) transistor and controls propagation of the compare data input, and the storage node data of a storage cell is used to control the passgate based on the storage node data. The CAM devices includes a PFET stack, having a first PFET and a second PFET, in communication with the transmission gate and the passgate, configured to compare the compare data input with the storage node data having the second logic state.

First claim

What is claimed is:

1. A content addressable memory (“CAM”) device having one or more comparators, comprising:
a transmission gate, having a positive field effect transistor (“PFET”) and a negative field effect transistor (“NFET”), configured to compare a compare data input with storage node data having a first logic state;
a passgate, in communication with the transmission gate, configured to compare the compare data input having a first logic state with the storage node data having a second logic state, wherein the passgate is an n-channel metal oxide semiconductor (NMOS) transistor and controls propagation of the compare data input; and
a PFET stack, having a first PFET and a second PFET, in communication with the transmission gate and the passgate, configured to compare the compare data input with the storage node data having the second logic state, wherein the transmission gate and the PFET stack are mutually exclusive.

2. The CAM device of claim 1 , wherein the transmission gate is turned on and the PFET stack is turned off for comparing the compare data input based on the storage node data having the first logic state.

3. The CAM device of claim 1 , wherein the transmission gate is turned off and the PFET stack is turned on for comparing the compare data input based on the storage node data having the second logic state.

4. The CAM device of claim 1 , wherein the passgate is turned on and the second PFET of the PFET stack is turned off for comparing the compare data input based on the compare data input having the first logic state and the storage node data having the second logic state, wherein the passgate passes the second logic state of the storage node data in an output propagation path indicating the compare data input fails to match the storage node data.

5. The CAM device of claim 1 , wherein the passgate is turned off and the PFET stack is turned on for comparing the compare data input based on the compare data input having the second logic state and the storage node data having the second logic state, wherein the PFET stack indicates the compare data input matches the storage node data.

6. The CAM device of claim 1 , wherein an output propagation path of the transmission gate is gated through the PFET based upon the compare data input having the first logic state, wherein the first logic state is passed through the output propagation path indicating the compare data input matches the storage node data.

7. The CAM device of claim 1 , wherein an output propagation path of the transmission gate is gated through the NFET based upon the compare data input having the second logic state, wherein the second logic state is passed through the output propagation path indicating the compare data input fails to match the storage node data.

8. The CAM device of claim 1 , wherein an output propagation path of the compare data input passes through the PFET stack based upon the compare data input having the first logic state, wherein the compare data input matches the storage node data.

9. The CAM device of claim 1 , wherein the first logic state is a bit set to a value of 1 and the second logic state is a bet set to a value of zero.

10. A system for using a content addressable memory (“CAM”) device having one or more comparators in a computing environment, comprising one or more computers with executable instructions that when executing cause the system to:
compare a compare data input with storage node data having a first logic state using a transmission gate, having a positive field effect transistor (“PFET”) and a negative field effect transistor (“NFET”);
compare the compare data input having a first logic state with the storage node data having a second logic state using a passgate, wherein the passgate is an n-channel metal oxide semiconductor (NMOS) transistor; and
compare the compare data input with the storage node data having the second logic state using a PFET stack, having a first PFET and a second PFET, wherein the transmission gate and the PFET stack are mutually exclusive.

11. The system of claim 10 , wherein the transmission gate is turned on and the PFET stack is turned off for comparing the compare data input based on the storage node data having the first logic state, and wherein the transmission gate is turned off and the PFET stack is turned on for comparing the compare data input based on the storage node data having the second logic state, wherein the first logic state is a bit set to a value of 1 and the second logic state is a bet set to a value of zero.

12. The system of claim 10 , wherein the transmission gate is turned off and the PFET stack is turned on for comparing the compare data input based on the storage node data having the second logic state, wherein the first logic state is a bit set to a value of 1 and the second logic state is a bet set to a value of zero.

13. The system of claim 10 , wherein the passgate is turned on and the second PFET of the PFET stack is turned off for comparing the compare data input based on the compare data input having the first logic state and the storage node data having the second logic state, wherein the passgate passes the second logic state of the storage node data in an output propagation path indicating the compare data input fails to match the storage node data.

14. The system of claim 10 , wherein the passgate is turned off and the PFET stack is turned on for comparing the compare data input based on the compare data input having the second logic state and the storage node data having the second logic state, wherein the PFET stack indicates the compare data input matches the storage node data.

15. The system of claim 10 , wherein the executable instructions when executed cause the system to:
indicate the compare data input matches the storage node data using the PFET of the transmission gate based upon the compare data input having the first logic state and the storage node data having the first logic state; and
indicate the compare data input fails to match the storage node data using the NFET of the transmission gate based upon the compare data input having the second logic state and the storage node data having the first logic state.

16. The system of claim 10 , wherein the executable instructions when executed cause the system to:
indicate the compare data input matches the storage node data using the PFET stack based upon the compare data input having the second logic state and the storage node data having the second logic state; and
indicate the compare data input fails to match the storage node data using the passgate based upon the compare data input having the first logic state and the storage node data having the second logic state.

17. A computer program product for using a content addressable memory (“CAM”) device having one or more comparators in a computing environment, the computer program product comprising one or more computer readable storage media, and program instructions collectively stored on the one or more computer readable storage media, the program instruction comprising:
program instructions to compare a compare data input with storage node data having a first logic state using a transmission gate, having a positive field effect transistor (“PFET”) and a negative field effect transistor (“NFET”);
program instructions to compare the compare data input having a first logic state with the storage node data having a second logic state using a passgate, wherein the passgate is an n-channel metal oxide semiconductor (NMOS) transistor; and
program instructions to compare the compare d

Assignees

• IBM

Inventors

• Ramamurthy Hema
• Lee Michael

Classifications

• G11C15/04 Primary

  using semiconductor elements · CPC title

• G11C7/12

  Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines · CPC title

• G11C11/419

  Read-write [R-W] circuits · CPC title