Operation module and method thereof

Patent metadata

Field	Value
Publication number	US-11836497-B2
Application number	US-201816075836-A
Country	US
Kind code	B2
Filing date	Jul 23, 2018
Priority date	Feb 5, 2018
Publication date	Dec 5, 2023
Grant date	Dec 5, 2023

Abstract

There is provides an operation module, which includes a memory, a register unit, a dependency relationship processing unit, an operation unit, and a control unit. The memory is configured to store a vector, the register unit is configured to store an extension instruction, and the control unit is configured to acquire and parse the extension instruction, so as to obtain a first operation instruction and a second operation instruction. An execution sequence of the first operation instruction and the second operation instruction can be determined, and an input vector of the first operation instruction can be read from the memory. The operation unit is configured to convert an expression mode of the input data index of the first operation instruction and to screen data, and to execute the first and second operation instruction according to the execution sequence, so as to obtain an extension instruction.

First claim

What is claimed is:

1. An operation module, applicable to execute operations according to an extension instruction, comprising a memory, an operation unit, and a control unit; wherein the control unit, is configured to:
acquire the extension instruction that includes an opcode and one or more opcode domains,
parse the extension instruction to obtain a first operation instruction and a second operation instruction,
wherein the first operation instruction includes a first operation instruction identifier that identifies the first operation instruction, an input data address of a first operation instruction, and an output data address of the first operation instruction,
wherein the second operation instruction includes a second operation instruction identifier that identifies the second operation instruction, an input data address of the second operation instruction, and an output data address of the second operation instruction, and
wherein the first operation instruction identifier is indicated by the opcode;
determine an execution sequence of the first operation instruction and the second operation instruction according to the first operation instruction and the second operation instruction; and
read input data of the first operation instruction corresponding to the input data address of the first operation instruction from the memory according to the input data address of the first operation instruction; and
the operation unit, is configured to:
convert an expression mode of an input data index of the first operation instruction, so as to obtain the input data index of the first operation instruction in a default indexing expression mode;
screen the input data of the first operation instruction according to the input data index of the first operation instruction in the default indexing expression mode; and
execute the first operation instruction and the second operation instruction for the input data of the first operation instruction and input data of the second operation instruction respectively according to the execution sequence, so as to obtain an operation result.

2. The operation module of claim 1 , wherein the operation unit comprises an index processing unit, which is configured to:
determine whether the expression mode of the input data index of the first operation instruction is a default indexing expression mode;
convert the expression mode of the input data index of the first operation instruction into the default indexing expression mode according to a converting instruction, based on a determination that the expression mode of the input data index of the first operation instruction is not the default expression mode, so as to obtain the input data index of the first operation instruction in the default indexing expression mode; and to
screen the input data of the first operation instruction according to the input data index of the first operation instruction in the default indexing expression mode, so as to obtain the input data of the first operation instruction.

3. The operation module of claim 2 , wherein the expression mode of the input data index of the first operation instruction comprises a direct indexing expression mode, a step indexing expression mode, a list of list (LIL) expression mode, a coordinate list (COO) expression mode, a compressed sparse row (CSR) expression mode, a compressed sparse column (CSC) expression mode, an Ellpack-ltpack (ELL) expression mode, and a hybrid (HYB) expression mode; and the default indexing expression mode comprises the direct indexing expression mode, the step indexing expression mode, the LIL expression mode, the COO expression mode, the CSR expression mode, the CSC expression mode, the ELL expression mode, and the HYB expression mode.

4. The operation module of claim 3 , wherein the input data of the first operation instruction is configured as sparse data, and when the input data index of the first operation instruction is expressed in the direct indexing expression mode, the input data index of the first operation instruction is a string consisting of 0's and l's, wherein the number 0 indicates that an absolute value of an element in the input data of the first operation instruction is less than or equal to a preset threshold, the number 1 indicates that an absolute value of an element in the input data of the first operation instruction is greater than the preset threshold.

5. The operation module according to claim 1 , further comprising:
a register unit, configured to store the extension instruction;
a dependency relationship processing unit, configured to determine whether input data accessed by the extension instruction is the same as that accessed by a previous extension instruction prior to acquiring the extension instruction by the control unit; wherein a first operation instruction and a second operation instruction of a current extension instruction are provided to the operation unit when the previous extension instruction have been executed based on a determination that the input data accessed by the extension instruction is the same as that accessed by the previous extension instruction, and the first operation instruction and the second operation instruction of the current extension instruction are provided to the operation unit based on a determination that the input data accessed by the extension instruction is not the same as that accessed by the previous extension instruction;
wherein the dependency relationship processing unit is further configured to store the current extension instruction in a memory queue when the input data accessed by the extension instruction is the same as that accessed by the previous extension instruction, and to provide the current extension instruction in the memory queue to the control unit when the previous extension instruction have been executed.

6. The operation module of claim 5 , wherein the control unit comprises:
a fetch subunit, configured to obtain the extension instruction from the register unit;
a decoding subunit, configured to decode the extension instruction to obtain the first operation instruction, the second operation instruction, and the execution sequence;
an instruction queue subunit, configured to store the first operation instruction and the second operation instruction according to the execution sequence.

7. The operation module of claim 2 , wherein the operation unit further comprises a vector adder circuit, a vector multiplier circuit, a comparison circuit, a nonlinear operation circuit, and a vector-scalar multiplier circuit, wherein the operation unit is configured as a multi-pipeline architecture;
wherein the index processing unit is located at a first pipeline stage, the vector multiplier circuit and the vector-scalar multiplier circuit are located at a second pipeline stage, the comparison circuit and the vector adder circuit are located at a third pipeline stage, and the non-linear operation circuit is located at a fourth flow level, wherein an output data of the first pipeline stage is an input data of the second pipeline stage, an output data of the second pipeline stage is an input data of the third pipeline stage, and an output data of the third pipeline stage is an input data of the fourth pipeline stage.

8. The operation module of claim 7 , wherein the operation unit further comprises a conversion circuit, the conversion circuit is located at the second pipeline stage and the fourth pipeline stage, or the conversion circuit is located at the second pipeline stage, or the conversion circuit is located at the fourth pipeline stage.

9. The operation module of claim 1 , wherein the control unit is configured to:
determine whether an output data of the first operation instruction

Assignees

• Shanghai Cambricon Inf Tech Co Ltd

Inventors

• Wang Bingrui
• Zhou Shengyuan
• Zhang Yao

Classifications

• G06N3/0495

  Quantised networks; Sparse networks; Compressed networks · CPC title

• G06N3/0464

  Convolutional networks [CNN, ConvNet] · CPC title

• G06F9/30036

  Instructions to perform operations on packed data, e.g. vector, tile or matrix operations · CPC title

• G06F9/30181 Primary

  Instruction operation extension or modification · CPC title

• G06F9/3001

  Arithmetic instructions · CPC title