Memory system with cached memory module operations

Patent metadata

Field	Value
Publication number	US-11836099-B2
Application number	US-202117548510-A
Country	US
Kind code	B2
Filing date	Dec 11, 2021
Priority date	Oct 1, 2015
Publication date	Dec 5, 2023
Grant date	Dec 5, 2023

Abstract

Memory controllers, devices, modules, systems and associated methods are disclosed. In one embodiment, a memory module includes a pin interface for coupling to a bus. The bus has a first width. The module includes at least one storage class memory (SCM) component and at least one DRAM component. The memory module operates in a first mode that utilizes all of the first width, and in a second mode that utilizes less than all of the first width.

First claim

We claim:

1. A memory module, comprising:
memory including at least one memory component;
buffer circuitry, the buffer circuitry configured to buffer operations between the memory and a memory controller, the buffer circuitry including:
a primary interface for communicating directly with the memory controller;
a secondary interface for communicating with the at least one memory component;
a backchannel interface for establishing a backchannel link between the memory module and a second memory module; and

wherein the memory module receives data for writing to the at least one memory component from the second memory module via the backchannel link.

2. The memory module of claim 1 , wherein the buffer circuitry includes:
data buffer circuitry; and
wherein the backchannel interface includes backchannel data interface circuitry to transfer data between the data buffer circuitry and the second memory module.

3. The memory module of claim 1 , wherein the buffer circuitry includes:
address buffer circuitry; and
wherein the backchannel interface includes backchannel address interface circuitry to transfer command/address (C/A) information between the address buffer circuitry and the second memory module.

4. The memory module of claim 1 , wherein:
the primary interface is to communicate directly with the memory controller via a point-to-point link.

5. The memory module of claim 1 , wherein:
at least a portion of the memory is allocated as cache for operations involving the second memory module; and
wherein the backchannel interface is to carry out cache transfers between the memory module and the second memory module.

6. The memory module of claim 2 , wherein:
the backchannel interface is to transfer data between the memory controller and the memory module via the second memory module.

7. The memory module of claim 6 , wherein:
for a full transfer bandwidth configuration, all data transfer associated with the memory controller are directed to the memory module.

8. A buffer circuit for use on a memory module to buffer operations between memory disposed on the memory module and a memory controller, the buffer circuit comprising:
a primary interface including a primary input/output (I/O) circuit for communicating with the memory controller over a primary signaling path;
a secondary interface including a secondary I/O circuit for communicating with the at least one memory component of the memory over a secondary signaling path;
backchannel interface circuitry for establishing a backchannel link between the memory module and a second memory module; and
wherein the backchannel interface circuitry receives data for writing to the at least one memory component from the second memory module.

9. The buffer circuit of claim 8 , wherein:
the primary interface comprises a primary data interface;
the secondary interface comprises a secondary data interface; and
wherein the primary data interface, the secondary data interface, and the backchannel interface circuitry are formed on at least one data buffer integrated circuit (IC) chip.

10. The buffer circuit of claim 8 , wherein:
the primary interface comprises a primary command/address (C/A) interface;
the secondary interface comprises a secondary C/A interface; and
wherein the primary C/A interface, the secondary C/A interface, and the backchannel interface circuitry are formed on at least one address buffer integrated circuit (IC) chip.

11. The buffer circuit of claim 8 , wherein:
the primary interface is to communicate directly with the memory controller via a point-to-point link.

12. The buffer circuit of claim 8 , wherein:
the backchannel interface circuitry is to cache transfers between the memory module and the second memory module.

13. The buffer circuit of claim 8 , wherein:
the backchannel interface circuitry is to transfer data between the memory controller and the memory module the second memory module.

14. The buffer circuit of claim 8 , wherein:
the backchannel interface circuitry is to balance electrical loading between (1) the memory controller and the memory module, and (2) the memory controller and the second memory module.

15. A method of operating a buffer circuit, the method comprising:
communicating with a memory controller via a primary interface;
communicating with at least one memory component of a memory over a secondary interface; and
establishing a backchannel link between a first memory module and a second memory module via a backchannel interface; and
receiving data for writing to the at least one memory component from the second memory module via the backchannel interface.

16. The method of claim 15 , wherein:
the communicating with a memory controller via a primary interface includes transferring data via a primary data path; and
the communicating with at least one memory component of a memory over a secondary interface includes transferring the data via a secondary data path.

17. The method of claim 15 , wherein:
the communicating with a memory controller via a primary interface includes transferring command/address (C/A) information via a primary C/A path; and
the communicating with at least one memory component of a memory over a secondary interface includes transferring the C/A information via a secondary C/A path.

18. The method of claim 15 , wherein the communicating with the memory controller comprises:
configuring the primary interface to communicate with the memory controller via a point-to-point link.

19. The method of claim 15 , wherein establishing the backchannel link further comprises:
transacting cache transfers between the memory module and the second memory module.

20. The method of claim 15 , wherein establishing the backchannel link further comprises:
balancing electrical loading between (1) the memory controller and the memory module, and (2) the memory controller and the second memory module.

Assignees

• Rambus Inc

Inventors

• Ware Frederick A
• Wright Kenneth L
• Linstadt John Eric
• Hampel Craig

Classifications

• G06F13/1678 Primary

  using bus width · CPC title

• G06F3/0604 Primary

  Improving or facilitating administration, e.g. storage management · CPC title

• G06F3/0613

  in relation to throughput · CPC title

• G06F3/0619

  in relation to data integrity, e.g. data losses, bit errors · CPC title

• G06F3/0634

  by changing the state or mode of one or more devices · CPC title