Display panel, manufacturing method thereof, and display device

Patent metadata

Field	Value
Publication number	US-11835825-B2
Application number	US-202117500233-A
Country	US
Kind code	B2
Filing date	Oct 13, 2021
Priority date	Feb 5, 2021
Publication date	Dec 5, 2023
Grant date	Dec 5, 2023

Abstract

The present disclosure provides a display panel, a manufacturing method thereof, and a display device. The display panel includes: a first substrate and a second substrate arranged opposite to each other, and a first spacer located between the first substrate and the second substrate, both ends of the first spacer are in contact with the first substrate and the second substrate respectively; a surface of the first substrate close to the second substrate includes a recess, and an end of the first spacer in contact with the first substrate is embedded in the recess.

First claim

What is claimed is:

1. A display panel, comprising a first substrate and a second substrate opposite to each other, and a first spacer between the first substrate and the second substrate,
wherein one end of the first spacer is in contact with the first substrate and the other end of the first spacer is in contact with the second substrate;
a surface of the first substrate close to the second substrate comprises a recess, and the end of the first spacer in contact with the first substrate is embedded in the recess;
the display panel further comprises a gate line, a common electrode line, a data line, a gate lead-in line, and a common electrode lead-in line, the gate lead-in line is configured to lead a scan signal into a corresponding gate line, and the common electrode lead-in line is configured to lead a common signal into a corresponding common electrode line;
the first substrate comprises a first base substrate, and a first signal line and a second signal line on the first base substrate, and an orthographic projection of the recess on the first base substrate is between orthographic projections of the first signal line and the second signal line on the first base substrate; and
each of the first signal line and the second signal line is one of the gate line, the common electrode line, the data line, the gate lead-in line, and the common electrode lead-in line.

2. The display panel of claim 1 , wherein
the first substrate further comprises a protective layer on a side of the first signal line and the second signal line away from the first base substrate;
the protective layer comprises a first portion on the first signal line and the second signal line, and a second portion between the first signal line and the second signal line;
a distance between a surface of the second portion facing the second substrate and the first base substrate is smaller than a distance between a surface of the first portion facing the second substrate and the first base substrate; and
the surface of the second portion facing the second substrate is the recess.

3. The display panel of claim 1 , wherein
a first edge of the orthographic projection of the recess on the first base substrate overlaps with an edge, close to the recess, of an orthographic projection of the first signal line on the first base substrate, and
a second edge, opposite to the first edge, of the orthographic projection of the recess on the first base substrate overlaps with an edge, close to the recess, of an orthographic projection of the second signal line on the first base substrate.

4. The display panel of claim 1 , wherein
the first signal line and the second signal line extend in a same direction.

5. The display panel of claim 4 , wherein
the display panel has a plurality of sub-pixel regions and an inter-sub-pixel region between adjacent sub-pixel regions, and
the first signal line, the second signal line, and the recess are all in the inter-sub-pixel region.

6. The display panel of claim 5 , wherein
the gate line, the common electrode line, the data line, the gate lead-in line, and the common electrode lead-in line are in the inter-sub-pixel region; and
the gate line and the common electrode line extend in a first direction, and the data line, the gate lead-in line, and the common electrode lead-in line extend in a second direction intersecting the first direction.

7. The display panel of claim 6 , wherein
the gate lead-in line is coupled to the gate line through a first via hole, and the common electrode lead-in line is coupled to the common electrode line through a second via hole.

8. The display panel of claim 6 , wherein
the first substrate further comprises a thin film transistor in the sub-pixel region and on the first base substrate; and
the thin film transistor comprises an active layer, a gate insulating layer, a gate electrode, an interlayer insulating layer, and a source-drain layer sequentially arranged along a direction away from the first base substrate.

9. The display panel of claim 8 , wherein
the gate line, the common electrode line, and the gate are arranged in a same layer and made of a same material; and
the data line, the gate lead-in line, the common electrode lead-in line, and the source-drain layer are arranged in a same layer and made of a same material.

10. The display panel of claim 8 , wherein
the first substrate further comprises a pixel electrode and a common electrode in the sub-pixel region on the first base substrate; and
the pixel electrode and the common electrode both comprise strip-shaped electrodes, and are alternately arranged.

11. The display panel of claim 10 , wherein
the pixel electrode, the common electrode, and the gate electrode are arranged in a same layer and made of a same material.

12. The display panel of claim 10 , wherein
the first substrate further comprises: a color filter in the sub-pixel region on the first base substrate; and
the pixel electrode and the common electrode are both on a side of the color filter away from the first base substrate.

13. The display panel of claim 5 , wherein
the second substrate comprises: a second base substrate, and a black matrix on a side of the second base substrate close to the first base substrate; and
the black matrix is in the inter-sub-pixel region, and an orthographic projection of the black matrix on the first base substrate at least partially overlaps with the orthographic projections of the first signal line and the second signal line on the first base substrate.

14. The display panel of claim 1 , wherein
from a plan view of the display panel, the recess is between the gate lead-in line and the common electrode lead-in line.

15. The display panel of claim 1 , wherein
from a plan view of the display panel, the recess is between the data line and the gate lead-in line.

16. The display panel of claim 1 , wherein
the display panel further comprises a second spacer between the first substrate and the second substrate;
a height of the second spacer is smaller than a height of the first spacer; and
one end of the second spacer is in contact with one of the first substrate and the second substrate, and the other end of the second spacer is suspended.

17. A display device comprising a display panel, wherein
the display panel comprises: a first substrate and a second substrate opposite to each other, and a first spacer between the first substrate and the second substrate;
one end of the first spacer is in contact with the first substrate and the other end of the first spacer is in contact with the second substrate;
a surface of the first substrate close to the second substrate comprises a recess, and the end of the first spacer in contact with the first substrate is embedded in the recess;
the display panel further comprises a gate line, a common electrode line, a data line, a gate lead-in line, and a common electrode lead-in line, the gate lead-in line is configured to lead a scan signal into a corresponding gate line, and the common electrode lead-in line is configured to lead a common signal into a corresponding common electrode line;
the first substrate comprises a first base substrate, and a first signal line and a second signal line on the first base substrate, and an orthographic projection of the recess on the first base substrate is between orthographic projections of the first signal line and the second signal line on the first base substrate; and
each of the first signal line and the second signal line is one of the gate line, the common electrode line, the d

Assignees

• Hefei Boe Display Tech Co Ltd
• Boe Technology Group Co Ltd

Inventors

• Liu Qi
• Zhang Wei
• Wang Xipeng
• Gao Jilei
• Zhang Yonggang
• Zhou Xin
• Li Chao
• Li Bin
• Xu Benzhi

Classifications

• G02F1/13392 Primary

  spacers dispersed on the cell substrate, e.g. spherical particles, microfibres · CPC title

• G02F1/136209

  Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element · CPC title

• G02F1/136286

  Wiring, e.g. gate line, drain line · CPC title

• G02F1/13394 Primary

  spacers regularly patterned on the cell subtrate, e.g. walls, pillars (G02F1/133377 takes precedence) · CPC title

• G02F1/13396

  Spacers having different sizes · CPC title