Systems and methods for timing recovery with bandwidth extension

Patent metadata

Field	Value
Publication number	US-11831747-B2
Application number	US-202217589159-A
Country	US
Kind code	B2
Filing date	Jan 31, 2022
Priority date	Apr 28, 2020
Publication date	Nov 28, 2023
Grant date	Nov 28, 2023

Abstract

A receiver includes a feed-forward equalizer, a first detector, a jitter estimation circuit, and a jitter mitigation circuit. The feed-forward equalizer is configured to equalize channel gain of digitized samples of a received signal and to output equalized samples. The first detector is configured to detect symbols in the equalized samples. The jitter estimation circuit is configured to estimate jitter in the equalized samples by estimating a deviation in periodicity between pairs of the equalized samples. The jitter mitigation circuit comprises a linearized FIR filter configured to receive an input including the equalized samples or the detected symbols and to compensate inter symbol interference in the equalized samples due to the jitter as a function of the estimated jitter and an estimate of the inter symbol interference.

First claim

What is claimed is:

1. A receiver comprising:
a feed-forward equalizer configured to equalize channel gain of digitized samples of a received signal and to output equalized samples;
a first detector configured to detect symbols in the equalized samples;
a jitter estimation circuit configured to estimate jitter in the equalized samples; and
a jitter mitigation circuit comprising:
a linearized FIR filter configured to receive an input including the equalized samples or the detected symbols and to compensate inter symbol interference in the equalized samples due to the jitter as a function of the estimated jitter and an estimate of the inter symbol interference;
an error generator configured to generate an error signal based on the detected symbols and an output of the jitter mitigation circuit; and
a second detector configured to generate the estimated of jitter based on the error signal and one of (i) the detected symbols and (ii) the estimate of the inter symbol interference.

2. A receiver comprising:
a feed-forward equalizer configured to equalize channel gain of digitized samples of a received signal and to output equalized samples;
a first detector configured to detect symbols in the equalized samples;
a jitter estimation circuit configured to estimate jitter in the equalized samples; and
a jitter mitigation circuit comprising:
a linearized FIR filter configured to receive an input including the equalized samples or the detected symbols and to compensate inter symbol interference in the equalized samples due to the jitter as a function of the estimated jitter and an estimate of the inter symbol interference;
a multiplier configured to multiply an output of the linearized FIR filter by the estimated jitter to generate the estimate of the inter symbol interference; and
a subtractor configured to subtract the estimate of the inter symbol interference from the equalized samples to generate an output signal with reduced inter symbol interference.

3. The receiver of claim 2 wherein the output signal is fed back to the jitter estimation circuit and wherein the jitter mitigation circuit reduces latency of the jitter estimation circuit by estimating the inter symbol interference and subtracting the estimate of the inter symbol interference from the equalized samples outside the jitter estimation circuit.

4. A receiver comprising:
a feed-forward equalizer configured to equalize channel gain of digitized samples of a received signal and to output equalized samples;
a first detector configured to detect symbols in the equalized samples;
a jitter estimation circuit configured to estimate jitter in the equalized samples; and
a jitter mitigation circuit comprising a linearized FIR filter configured to receive an input including the equalized samples or the detected symbols and to compensate inter symbol interference in the equalized samples due to the jitter as a function of the estimated jitter and an estimate of the inter symbol interference,
wherein the linearized FIR filter comprises a plurality of delay lines connected to each other in series and wherein outputs of the respective delay lines are multiplied by respective coefficients and summed to generate an output that is scaled by the estimated jitter to generate the estimate of the inter symbol interference.

5. The receiver of claim 4 further comprising a subtractor configured to subtract the estimate of the inter symbol interference from the equalized samples to generate an output signal with reduced inter symbol interference.

6. A method for a receiver comprising:
generating equalized samples by equalizing channel gain of digitized samples of a received signal;
detecting symbols in the equalized samples;
estimating jitter in the equalized samples;
processing, using a linearized FIR filter, an input including the equalized samples or the detected symbols;
compensating, based on the processing, inter symbol interference in the equalized samples due to the jitter as a function of the estimated jitter and an estimate of the inter symbol interference and to provide an output signal;
generating an error signal based on the detected symbols and an output of the linearized filter; and
generating the estimated jitter based on the error signal and one of (i) the detected symbols and (ii) the estimate of the inter symbol interference.

7. A method for a receiver comprising:
generating equalized samples by equalizing channel gain of digitized samples of a received signal;
detecting symbols in the equalized samples;
estimating jitter in the equalized samples;
processing, using a linearized FIR filter, an input including the equalized samples or the detected symbols;
compensating, based on the processing, inter symbol interference in the equalized samples due to the jitter as a function of the estimated jitter and an estimate of the inter symbol interference;
generating the estimate of the inter symbol interference by multiplying an output of the linearized FIR filter by the estimated jitter; and
generating an output signal with reduced inter symbol interference by subtracting the estimate of the inter symbol interference from the equalized samples.

8. The method of claim 7 further comprising:
estimating the jitter based on the output signal; and
reducing latency of a circuit estimating the jitter by estimating the inter symbol interference and subtracting the estimate of the inter symbol interference from the equalized samples outside the circuit.

9. A method for a receiver comprising:
generating equalized samples by equalizing channel gain of digitized samples of a received signal;
detecting symbols in the equalized samples;
estimating jitter in the equalized samples;
processing, using a linearized FIR filter, an input including the equalized samples or the detected symbols; and
compensating, based on the processing, inter symbol interference in the equalized samples due to the jitter as a function of the estimated jitter and an estimate of the inter symbol interference;
wherein the linearized FIR filter comprises a plurality of delay lines connected to each other in series, the method further comprising:
multiplying outputs of the respective delay lines by respective coefficients;
generating an output by combining the multiplied outputs; and
generating the estimate of the inter symbol interference by scaling the output by the estimated jitter.

10. The method of claim 9 further comprising generating an output signal with reduced inter symbol interference by subtracting the estimate of the inter symbol interference from the equalized samples.

Assignees

• Marvell Asia Pte Ltd

Inventors

• Smith Benjamin
• Riani Jamal

Classifications

• H04L7/0062 Primary

  detection of error based on data decision error, e.g. Mueller type detection · CPC title

• H04L1/205

  jitter monitoring · CPC title

• H04L7/0029

  interpolation of received data signal · CPC title

• H04L7/0087

  Preprocessing of received signal for synchronisation, e.g. by code conversion, pulse generation or edge detection · CPC title

• H04B1/16 Primary

  Circuits · CPC title