Data compressor logic circuit

Patent metadata

Field	Value
Publication number	US-11831341-B2
Application number	US-202017001580-A
Country	US
Kind code	B2
Filing date	Aug 24, 2020
Priority date	Oct 25, 2018
Publication date	Nov 28, 2023
Grant date	Nov 28, 2023

Abstract

A compressor includes a logic circuit having transistors of a first channel type to receive a plurality of bit signals, and transistors of a second channel type, different from the first channel type, to receive the plurality of bit signals. The transistors of the first channel type are configured to generate an XOR logic output based on the plurality of bit signals, and the transistors of the second channel type are configured to generate, substantially simultaneous with the generation of the XOR logic output, an XNOR logic output based on the plurality of bit signals. The compressor includes NAND gates to receive multiplicand and multiplier bit signals.

First claim

What is claimed is:

1. A logic circuit, comprising:
a first input terminal for receiving a first operand;
a first switch having a gate terminal, wherein the gate terminal of the first switch is electrically coupled to the first input terminal;
a first output terminal electrically coupled to a first terminal of the first switch;
a second input terminal for receiving a second operand, wherein the second input terminal is electrically coupled to a second terminal of the first switch,
a second switch having a first terminal, wherein the first terminal of the second switch is electrically coupled to a first terminal of a third switch, wherein the first terminal of the third switch is electrically coupled to a gate terminal of a fourth switch, wherein the first and second operands are transmitted at three different respective input terminals, and wherein a gate terminal of the second switch is electrically coupled to the second input terminal.

2. The logic circuit of claim 1 , wherein a third input terminal is electrically coupled to the first output terminal, wherein the first and second operands are transmitted at solely three different respective input terminals, and wherein third and fourth operands are transmitted at solely two different respective input terminals.

3. The logic circuit of claim 1 , wherein
the first terminal of the second switch is electrically coupled to the first terminal of the first switch and the first output terminal.

4. The logic circuit of claim 1 , wherein the first and second switches are both n-channel type or p-channel type transistors.

5. A logic circuit, comprising:
a first input terminal for receiving a first operand;
a first switch having a gate terminal, wherein the gate terminal of the first switch is electrically coupled to the first input terminal;
a first output terminal electrically coupled to a first terminal of the first switch;
a second input terminal for receiving a second operand, wherein the second input terminal is electrically coupled to a second terminal of the first switch;
a second switch having a first terminal, wherein the first terminal of the second switch is electrically coupled to the second terminal of the first switch;
a third switch having a terminal, wherein the terminal of the third switch is electrically coupled to a second terminal of the second switch;
a third input terminal for receiving the first operand electrically coupled between the first terminal of the first switch and the first output terminal; and
a second output terminal electrically coupled to the terminal of the third switch.

6. The logic circuit of claim 1 , wherein the first switch is a first transistor of a first channel type, and the second switch is a second transistor of a second channel type, different from the first channel type.

7. The logic circuit of claim 1 , wherein the third switch is a first transistor of a first channel type, and the fourth switch is a second transistor of a second channel type, different from the first channel type.

8. The logic circuit of claim 1 , further comprising:
first and second transistors, connected in series between the first output terminal and a voltage supply terminal.

9. The logic circuit of claim 8 , wherein the voltage supply terminal is electrically coupled to a reference voltage.

10. The logic circuit of claim 1 , further comprising:
first and second transistors connected in series between the first output terminal and ground.

11. A circuit, comprising:
input terminals for receiving first, second, third, and fourth operands;
first and second output terminals for transmitting respective first and second output data signals; and
logic circuitry coupled to the input and output terminals, wherein the first output data signal is a logic complement of the second output data signal, wherein respective transistors receiving the first and third operands are coupled between a ground voltage and a conductor transmitting the first output signal,
wherein the logic circuitry comprises ten input terminals, and wherein each of the second and fourth operands are received at two of the input terminals, wherein respective transistors configured to receive the second and fourth operands are coupled in series between either a first output terminal and ground or a second output terminal and ground, and wherein:
first, second, and third input terminals are solely configured to receive to the first operand;
fourth, fifth, and sixth input terminals are configured to receive the third operand;
seventh and eighth input terminals are configured to receive the second operand, and
ninth and tenth input terminals are configured to receive the fourth operand.

12. The circuit of claim 11 , wherein the first operand is a complement of the second operand, and wherein the third operand is a complement of the fourth operand, wherein the fourth, the fifth, and the sixth input terminals are solely configured to receive the third operand.

13. The circuit of claim 11 , wherein the logic circuitry comprises:
first, second, third, and fourth switches, wherein gate terminals of the first and fourth switches are electrically coupled to the first operand, wherein gate terminals of the second and third switches are electrically coupled to the third operand, and wherein the seventh and the eighth input terminals are solely configured to receive the second operand.

14. The circuit of claim 11 , wherein the logic circuitry is configured to perform XOR and XNOR operations of the operands, and wherein the ninth and the tenth input terminals are solely configured to receive the fourth operand.

15. A method comprising:
receiving first, second, third and fourth input signals at input terminals of a circuit; and
sending, from the circuit, first and second output signals corresponding to respective XOR and XNOR operations of the first, second, third, and forth input signals, wherein the circuit comprises first, second, third, and fourth switches, wherein a gate terminal of the first switch is electrically coupled to a first terminal, wherein a second terminal of a second switch is electrically coupled to a first terminal of third switch, wherein the first terminal of third switch is electrically coupled to a gate terminal of a fourth switch, and wherein the first and third input signals are transmitted at solely three different respective input terminals.

16. The method of claim 15 , wherein the XOR operation is a first logic data value when the first and third signals or the second and fourth signals comprise same logic states, wherein the XNOR operation is a second logic data value when the first and third signals or the second and fourth signals comprise different logic states, wherein the first and second logic data values are different, and wherein the second and fourth input signals are solely transmitted at solely two different respective input terminals.

Assignees

• Advanced Risc Mach Ltd

Inventors

• Shekhar Shardendu
• Chen Andy Wangkun
• Chong Yew Keong

Classifications

• H03M7/005 Primary

  using semiconductor devices · CPC title

• H03K19/0944 Primary

  using MOSFET {or insulated gate field-effect transistors, i.e. IGFET}(H03K19/096 takes precedence) · CPC title

• H03K19/20 Primary

  characterised by logic function, e.g. AND, OR, NOR, NOT circuits (H03K19/003 - H03K19/01 take precedence) · CPC title

• H03K19/215

  using field-effect transistors · CPC title

• H03M7/6011

  Encoder aspects · CPC title