Burst error tolerant decoder and related systems, methods, and devices

Patent metadata

Field	Value
Publication number	US-11831340-B2
Application number	US-202117453119-A
Country	US
Kind code	B2
Filing date	Nov 1, 2021
Priority date	Oct 1, 2018
Publication date	Nov 28, 2023
Grant date	Nov 28, 2023

Abstract

Disclosed embodiments of the present disclosure relate, generally, to systems, methods, and devices for correction of burst-errors induced during transmission of encoded blocks of information. Some embodiments relate to decoders configured to test candidate corrections on a received block of information and select a candidate correction that best fits the characteristics of burst-errors expected for a type of transmission scheme. Such tested candidate corrections may be selected based on characteristics of burst-errors typically induced for a type of transmission scheme. Some embodiments relate to decoders configured to test candidate corrections for correcting burst-errors and perform standard error correcting techniques such as Reed-Solomon forward error correction techniques. Some embodiments relate to systems, such as serial/deserializer interfaces, that incorporate such decoders.

First claim

What is claimed is:

1. A transmission interface that is burst-error tolerant, the transmission interface comprising:
a transmitter to sequentially provide a forward error correction (FEC) encoded transmission block to a physical transmission line; and
a receiver to:
receive the FEC encoded transmission block from the physical transmission line;
detect, via multiple candidate correction patterns, bits of the received FEC encoded transmission block that exhibit characteristics indicative of burst errors induced in the FEC encoded transmission block during transmission over the physical transmission line; and
change at least some of the detected bits.

2. The transmission interface of claim 1 , wherein the receiver comprises a burst error decoder, wherein the burst error decoder tests candidate correction patterns for correcting errors in contiguous bits on the received FEC encoded transmission block.

3. The transmission interface of claim 2 , wherein the receiver comprises a standard error correction decoder, wherein the standard error correction decoder applies a standard error correction protocol on the received FEC encoded transmission block, and wherein the receiver selects one of a result of the standard error correction circuitry and a result of the burst error decoder.

4. The transmission interface of claim 3 , wherein the burst error decoder:
applies candidate correction patterns to the received FEC encoded transmission block; and
selects a candidate correction pattern having a closest determined relationship with a burst error.

5. The transmission interface of claim 4 , wherein the burst error decoder:
determines a score of a respective candidate correction pattern at least partially based on a correction result generated at least partially responsive to application of the respective candidate correction pattern to the received FEC encoded transmission block;
determines a score of a further respective candidate correction pattern at least partially based on a correction result generated at least partially responsive to application of the further respective candidate correction pattern to the received FEC encoded transmission block; and
selects a candidate correction pattern from one of the respective candidate correction pattern or the further respective candidate correction pattern.

6. The transmission interface of claim 2 , wherein the detected bits of the received FEC encoded transmission block are contiguous bits.

7. A transmission interface that is burst-error tolerant, the transmission interface comprising,
a transmitter to sequentially provide a forward error correction (FEC) encoded transmission block to a physical transmission line; and
a receiver to:
receive the FEC encoded transmission block from the physical transmission line;
detect, via test candidate correction patterns for correcting errors in contiguous bits on the received FEC encoded transmission block, bits of the received FEC encoded transmission block that exhibit characteristics indicative of partial burst errors induced in the FEC encoded transmission block during transmission over the physical transmission line; and
change at least some of the detected bits.

Assignees

• Microchip Tech Inc

Inventors

• Graumann Peter

Classifications

• H03M13/2906 Primary

  using block codes (H03M13/2957 takes precedence) · CPC title

• G06F11/1076

  Parity data used in redundant arrays of independent storages, e.g. in RAID systems · CPC title

• H03M13/17

  Burst error correction, e.g. error trapping, Fire codes · CPC title

• G06F11/1012 Primary

  using codes or arrangements adapted for a specific type of error (G06F11/1048 takes precedence) · CPC title

• H03M13/1515

  Reed-Solomon codes · CPC title