Semiconductor device

Patent metadata

Field	Value
Publication number	US-11830909-B2
Application number	US-202217651993-A
Country	US
Kind code	B2
Filing date	Feb 22, 2022
Priority date	Sep 17, 2019
Publication date	Nov 28, 2023
Grant date	Nov 28, 2023

Abstract

A semiconductor device is provided that includes a semiconductor substrate having a first main surface and a second main surface facing each other; a dielectric layer laminated on the first main surface of the semiconductor substrate; a first electrode layer laminated on the dielectric layer; and a protective layer covering at least an outer peripheral end of the dielectric layer and an outer peripheral end of the first electrode layer. Moreover, the protective layer is provided to expose an outer peripheral end on the first main surface of the semiconductor substrate. The semiconductor substrate includes a high-resistance region positioned at least directly under an outer peripheral end of the protective layer.

First claim

The invention claimed is:

1. A semiconductor device comprising:
a semiconductor substrate having a first main surface and a second main surface that oppose each other;
a dielectric layer disposed on the first main surface of the semiconductor substrate;
a first electrode layer disposed on the dielectric layer; and
a protective layer covering at least an outer peripheral end of the dielectric layer and an outer peripheral end of the first electrode layer, with the protective layer disposed to expose an outer peripheral end on the first main surface of the semiconductor substrate,
wherein the semiconductor substrate includes a high-resistance region positioned at least directly under an outer peripheral end of the protective layer, and
wherein a resistivity of the high-resistance region is 10 2 Ω·cm or more and 10 9 Ω·cm or less.

2. The semiconductor device according to claim 1 , wherein the high-resistance region is disposed closer to an outer peripheral end side of the semiconductor substrate than the outer peripheral end of the first electrode layer relative to a thickness direction of the semiconductor device.

3. The semiconductor device according to claim 2 , wherein the high-resistance region further extends to the outer peripheral end side of the semiconductor substrate from the outer peripheral end of the protective layer relative to the thickness direction of the semiconductor device.

4. The semiconductor device according to claim 1 , wherein the semiconductor substrate includes a low-resistance region other than where the high-resistance region is disposed in the semiconductor substrate.

5. The semiconductor device according to claim 4 , wherein a resistivity of the low-resistance region is 10 −5 Ω·cm or more and less than 10 2 Ω·cm.

6. The semiconductor device according to claim 1 , wherein the semiconductor substrate is a silicon substrate, and the high-resistance region is silicon oxide.

7. The semiconductor device according to claim 1 , further comprising at least one trench extending in the first main surface, wherein the dielectric layer is disposed along the trench.

8. The semiconductor device according to claim 7 , wherein the high-resistance region is disposed to have a depth smaller than a depth of the trench extending in a thickness direction of the semiconductor substrate.

9. The semiconductor device according to claim 2 , wherein the high-resistance region extends from the first main surface to the second main surface of the semiconductor substrate in the thickness direction.

10. The semiconductor device according to claim 1 , wherein the semiconductor substrate comprises a positive electrode, and the first electrode layer is a negative electrode.

11. The semiconductor device according to claim 1 , wherein the protective layer comprises an annular shape that covers the outer peripheral end of the dielectric layer and the outer peripheral end of the first electrode layer.

12. The semiconductor device according to claim 1 , wherein the outer peripheral end of the protective layer is disposed inside an outer peripheral surface of the first main surface of the semiconductor substrate and has an opening in a central portion thereof.

13. The semiconductor device according to claim 1 , wherein the high-resistance region comprises an annular shape so as to surround the first electrode layer in a plan view of the first main surface of the semiconductor substrate.

14. A semiconductor device comprising:
a semiconductor substrate having first and second main surfaces that oppose each other;
a dielectric layer disposed on the first main surface;
a first electrode layer disposed on the dielectric layer; and
a protective layer disposed on at least an outer peripheral end of the dielectric layer and an outer peripheral end of the first electrode layer,
wherein the semiconductor substrate includes a high-resistance region and a low-resistance region having a lower resistivity than a resistivity of the high-resistance region,
wherein the high-resistance region is disposed at least directly under an outer peripheral end of the protective layer, and
wherein the resistivity of the high-resistance region is 10 2 Ω·cm or more and 10 9 Ω·cm or less, and the resistivity of the low-resistance region is 10 −5 Ω·cm or more and less than 10 2 Ω·cm.

15. The semiconductor device according to claim 14 , wherein the protective layer is disposed to expose an outer peripheral end on the first main surface of the semiconductor substrate.

16. The semiconductor device according to claim 14 , further comprising:
at least one trench extending in the first main surface,
wherein the dielectric layer is disposed along the trench, and
wherein the high-resistance region is disposed to have a depth smaller than a depth of the trench extending in a thickness direction of the semiconductor substrate.

17. A semiconductor module comprising:
a DC power supply;
a switching device configured to turn on and off the DC power supply; and
the semiconductor device according to claim 1 , with the semiconductor device being connected to a positive electrode and a negative electrode of the DC power supply.

18. The semiconductor module according to claim 17 , wherein the semiconductor substrate of the semiconductor device is connected to the positive electrode of the DC power supply, and the first electrode layer of the semiconductor device is connected to the negative electrode of the DC power supply.

Assignees

• Murata Manufacturing Co

Inventors

• Ashimine Tomoyuki
• Irie Yuji
• Murase Yasuhiro

Classifications

• H10P30/209

  in silicon to make buried insulating layers · CPC title

• H10W74/137

  the encapsulations being directly on the semiconductor body (H10W74/134 takes precedence) · CPC title

• H10P30/208

  of electrically inactive species · CPC title

• H10P30/204 Primary

  into Group IV semiconductors · CPC title

• H10D1/665

  Trench conductor-insulator-semiconductor capacitors, e.g. trench MOS capacitors · CPC title