Image sensing device

Patent metadata

Field	Value
Publication number	US-11830893-B2
Application number	US-202117463310-A
Country	US
Kind code	B2
Filing date	Aug 31, 2021
Priority date	Sep 29, 2020
Publication date	Nov 28, 2023
Grant date	Nov 28, 2023

Abstract

An image sensing device is provided to include a pixel array having a plurality of pixels arranged in a matrix shape. Each of the pixels includes: a control node configured to generate a hole current in a substrate; a detection node configured to capture photocharge migrated by the hole current, formed in a shape whose at least part is partially open, and disposed to surround the control node, and a low resistance region including a dielectric layer formed in the substrate, and disposed in the opening on of the detection node. The low resistance region includes an inner low resistance region disposed between the control node and the center of the pixel.

First claim

What is claimed is:

1. An image sensing device, comprising:
a pixel array including a plurality of pixels arranged in a matrix shape,
wherein each of the plurality of the pixels is structured to respond to incident light to produce photocharge indicative of detected incident light and comprises:
a control node configured to receive a control signal for generating a current that carries the photocharge;
a detection node spaced from the control node and configured to have a shape that surrounds the control node and includes an opening, the detection node operable to capture the photocharge migrated by the current; and
a low resistance region disposed in the opening of the detection node, the low resistance region including a dielectric layer exhibiting a lower resistance than a resistance of the detection node,
wherein the low resistance region includes an inner low resistance region disposed between the control node and a center of the pixel.

2. The image sensing device of claim 1 , wherein the inner low resistance region is disposed on a straight line connecting the control node and the center of the pixel.

3. The image sensing device of claim 1 , wherein the low resistance region further comprises an outer low resistance region disposed between a vertex of the pixel and the control node.

4. The image sensing device of claim 3 , wherein the outer low resistance region is disposed on a straight line connecting the vertex of the pixel and the control node.

5. The image sensing device of claim 3 , wherein the inner low resistance region and the outer low resistance region are disposed on opposite sides of the control node to face each other.

6. The image sensing device of claim 1 , wherein the pixels further comprises:
a voltage stabilization area disposed at a vertex of the pixel; and
a pixel transistor area including at least one pixel transistor configured to process the photocharge generated in the pixel.

7. The image sensing device of claim 6 , wherein the voltage stabilization area abuts on a well region forming the body of the at least one pixel transistor and is configured to receive a voltage to disable a transfer of the photocharges.

8. The image sensing device of claim 6 , wherein the voltage stabilization area of the pixel is shared by the adjacent pixel in a row direction, column direction or diagonal direction of the pixel array.

9. The image sensing device of claim 1 , wherein the dielectric layer is disposed at a predetermined depth from one surface of the substrate.

10. The image sensing device of claim 1 , further comprising a depletion region disposed under the detection node,
wherein a depth of the depletion region from one surface of the substrate is larger than a depth of the dielectric layer of the low resistance region.

11. The image sensing device of claim 1 , wherein the control node, the detection node and the low resistance region are configured as a first tap structure and the pixel further includes second to fourth tap structures, each including a corresponding detection node and a corresponding control node.

12. The image sensing device of claim 11 , wherein the first and fourth tap structures are configured to receive a first demodulation control signal for generating the current, and
the second and third tap structures are configured to receive a second demodulation control signal for generating the current.

13. The image sensing device of claim 12 , wherein the first demodulation control signal has a first voltage level to enable a transfer of the photocharges and the second demodulation control signal has a second voltage level to disable the transfer of the photocharges, and
wherein the first and second demodulation control signals are out of phase with each other.

14. The image sensing device of claim 11 , wherein the first and fourth tap structures are disposed in a first diagonal direction passing through the center of the pixel, and
the second and third tap structures are disposed in a second diagonal direction different from the first diagonal direction and passing through the center of the pixel.

15. The image sensing device of claim 14 , wherein the low resistance regions of the first and fourth tap structures are disposed in the first diagonal direction, and
the low resistance regions of the second and third tap structures are disposed in the second diagonal direction.

16. The image sensing device of claim 1 , wherein each of the pixels further comprises a current path control area disposed in the center of the pixel.

17. The image sensing device of claim 16 , wherein the current path control area has a potential lower than that of the control node receiving a first voltage to enable a transfer of the photocharges, and higher than that of the control node receiving a second voltage to disable the transfer of the photocharge.

18. The image sensing device of claim 1 , wherein the detection node and the low resistance region form a ring shape to surround the control node.

19. The image sensing device of claim 1 , wherein, for the current, the low resistance region has lower resistance than the detection node.

Assignees

• Sk Hynix Inc

Inventors

• Yoon Hyung June
• Kim Jong Eun
• Kim Jong Chae
• Lee Jae Won
• Jang Jae Hyung
• Choi Hoon Moo

Classifications

• H10F39/18

  Complementary metal-oxide-semiconductor [CMOS] image sensors; Photodiode array image sensors · CPC title

• H10F39/807

  Pixel isolation structures · CPC title

• H10F39/803 Primary

  Pixels having integrated switching, control, storage or amplification elements · CPC title

• H10F39/8033 Primary

  Photosensitive area · CPC title

• H01L27/1461 Primary

  Electricity · mapped topic