Heated pins to couple with solder elements

US11830846B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11830846-B2
Application numberUS-201916424227-A
CountryUS
Kind codeB2
Filing dateMay 28, 2019
Priority dateMay 28, 2019
Publication dateNov 28, 2023
Grant dateNov 28, 2023

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  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Embodiments herein relate to systems, apparatuses, or processes for coupling or decoupling two substrates by heating pins on one of the substrates and either inserting or withdrawing the heated pins from solder elements on a BGA. In particular, by heating a plurality of pins on a first side of a first substrate, where the plurality of pins are substantially perpendicular to a plane of the substrate, inserting the heated plurality of pins into BGA attached to a second substrate where the BGA includes a plurality of solder elements aligned with the plurality of pins and where the heated plurality of pins melt the plurality of solder elements upon insertion. The inserted plurality of pins physically and/or electrically couple the first substrate and the second substrate.

First claim

Opening claim text (preview).

What is claimed is: 1. An apparatus comprising: a substrate with a first side and a second side opposite the first side; a plurality of pins on the first side of the substrate; a plurality of electric heaters embedded within the substrate, wherein the plurality of electric heaters are thermally coupled with the plurality of pins; a plurality of electrical input and electrical output pairs; and wherein each one of the plurality of electrical input and electrical output pairs is electrically coupled with a corresponding one of a plurality of subsets of the plurality of electric heaters. 2. The apparatus of claim 1 , wherein each one of the plurality of electric heaters is thermally coupled with a corresponding one of the plurality of pins. 3. The apparatus of claim 1 , wherein a subset of the plurality of electric heaters are thermally coupled with one of the plurality of pins. 4. The apparatus of claim 1 , wherein at least one of the plurality of pins includes a pad, wherein the pad is on the first side of the substrate, wherein the pad is directly thermally coupled with a pin, and wherein the pad surrounds at least one of the plurality of pins. 5. The apparatus of claim 1 , wherein the plurality of pins is substantially perpendicular to the first side of the substrate. 6. The apparatus of claim 1 , wherein the second side of the substrate includes a BGA to attach the substrate to another substrate. 7. A system comprising: a substrate including: a first side and a second side opposite the first side; a plurality of pins on the first side of the substrate that are substantially perpendicular to the first side of the substrate; a plurality of heaters embedded within the substrate, wherein the plurality of heaters are thermally coupled with the plurality of pins, and wherein a first subset of the plurality of heaters overlaps a second subset of the plurality of heaters with respect to a plane of the first side of the substrate; and wherein the plurality of pins, when heated, are to physically couple with or to physically decouple from a ball grid array (BGA) when the plurality of pins are inserted into or removed from the BGA; and a package with the BGA on a side of the package. 8. The system of claim 7 , wherein each one of the plurality of heaters is thermally coupled with a corresponding one or more of the plurality of pins. 9. The system of claim 8 , wherein the plurality of heaters are a plurality of electric heaters. 10. The system of claim 9 , further comprising one or more electrical connections coupled with the plurality of electric heaters. 11. The system of claim 7 , wherein the substrate or the package includes one or more alignment features to align the BGA of the package with the plurality of pins on the substrate. 12. The system of claim 7 , further comprising a controller tool physically coupled with the package to align the BGA with the plurality of pins or to facilitate heating of the plurality of pins during insertion or removal of the plurality of pins from the BGA. 13. The system of claim 12 , wherein the controller tool electrically couples with the plurality of heaters. 14. The system of claim 13 , wherein the plurality of pins include a selected one or more of: gold, tin, copper, iron, or nickel. 15. The system of claim 7 , wherein the plurality of pins are rods. 16. An apparatus comprising: a substrate with a first side and a second side opposite the first side; a plurality of pins on the first side of the substrate; a plurality of heaters embedded within the substrate, wherein the plurality of heaters are thermally coupled with the plurality of pins, and wherein a first subset of the plurality of heaters overlaps a second subset of the plurality of heaters with respect to a plane of the first side of the substrate. 17. The apparatus of claim 16 , wherein each one of the plurality of heaters is thermally coupled with a corresponding one of the plurality of pins. 18. The apparatus of claim 16 , wherein the plurality of heaters further include a plurality of electric heaters. 19. The apparatus of claim 18 , further comprising an electrical input and an electrical output coupled to the plurality of electric heaters. 20. The apparatus of claim 19 , wherein the electrical input and the electrical output further comprise a plurality of electrical input and electrical output pairs; and wherein each one of the plurality of electrical input and electrical output pairs is electrically coupled with a corresponding one of a plurality of subsets of the plurality of electric heaters. 21. The apparatus of claim 16 , wherein a subset of the plurality of heaters are thermally coupled with one of the plurality of pins. 22. The apparatus of claim 16 , wherein at least one of the plurality of pins includes a pad, wherein the pad is on the first side of the substrate, wherein the pad is directly thermally coupled with a pin, and wherein the pad surrounds at least one of the plurality of pins. 23. The apparatus of claim 16 , wherein the plurality of pins is substantially perpendicular to the first side of the substrate. 24. The apparatus of claim 16 , wherein the second side of the substrate includes a BGA to attach the substrate to another substrate.

Assignees

Inventors

Classifications

  • between stacked chips · CPC title

  • characterised by containers, encapsulations, or other housings for the stacked chips · CPC title

  • Package configurations · CPC title

  • H10W90/701Primary

    characterised by the relative positions of pads or connectors relative to package parts · CPC title

  • Arrangements for heating · CPC title

Patent family

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External sources

Frequently asked questions

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What does patent US11830846B2 cover?
Embodiments herein relate to systems, apparatuses, or processes for coupling or decoupling two substrates by heating pins on one of the substrates and either inserting or withdrawing the heated pins from solder elements on a BGA. In particular, by heating a plurality of pins on a first side of a first substrate, where the plurality of pins are substantially perpendicular to a plane of the subst…
Who is the assignee on this patent?
Intel Corp
What technology area does this patent fall under?
Primary CPC classification H10W90/701. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Nov 28 2023 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 2 related publications on this page (citations in our corpus or others sharing the same primary CPC).