Integrated circuits with line breaks and line bridges within a single interconnect level

Patent metadata

Field	Value
Publication number	US-11830768-B2
Application number	US-202117530777-A
Country	US
Kind code	B2
Filing date	Nov 19, 2021
Priority date	Dec 27, 2017
Publication date	Nov 28, 2023
Grant date	Nov 28, 2023

Abstract

Integrated circuit (IC) interconnect lines having line breaks and line bridges within one interconnect level that are based on a single lithographic mask pattern. Multi-patterning may be employed to define a grating structure of a desired pitch in a first mask layer. Breaks and bridges between the grating structures may be derived from a second mask layer through a process-based selective occlusion of openings defined in the second mask layer that are below a threshold minimum lateral width. Portions of the grating structure underlying openings defined in the second mask layer that exceed the threshold minimum lateral width are removed. Trenches in an underlayer may then be etched based on a union of the remainder of the grating structure and the occluded openings in the second mask layer. The trenches may then be backfilled to form the interconnect lines.

First claim

What is claimed is:

1. An integrated circuit (IC) device, comprising:
a plurality of first line segments comprising a conductive material, wherein the first line segments have a line width and adjacent ones of the first line segments are separated by a space width;
a dielectric material spacing apart ends of collinear ones of the first line segments by one or more first distances in a first lateral dimension; and
a plurality of second line segments comprising the conductive material, wherein:
the second line segments are in a same interconnect level as the first line segments and intersect two or more adjacent ones of the first line segments; and
the second line segments have end-to-end lengths in a second lateral dimension, orthogonal to the first lateral dimension, that are a first integer multiple of the line width summed with a second integer multiple of the space width.

2. The IC device of claim 1 , wherein the first distances are at least equal to the space width.

3. The IC device of claim 1 , wherein the space width is larger than the line width.

4. The IC device of claim 1 , wherein the first integer is at least two, and the second integer is at least one.

5. The IC device of claim 1 , wherein every line segment of one interconnect level of the IC device is either one of the first line segments or one of the second line segments.

6. The IC device of claim 1 , wherein each of the second line segments intersect two different adjacent ones of the first line segments over one or more second distances in the first lateral dimension.

7. The IC device of claim 6 , wherein at least some of the second distances are greater than at least some of the first distances.

8. The IC device of claim 7 , wherein the second distances are other than integer multiples of the first distances.

9. An integrated circuit (IC) device, comprising:
a plurality of transistors, individual ones of the transistors comprising one or more semiconductor materials; and
a plurality of interconnect levels interconnecting the transistors, wherein one or more of the plurality of the interconnect levels further comprise:
a plurality of first line segments comprising a conductive material, wherein the first line segments have a line width and adjacent ones of the first line segments are separated by a substantially equal space width;
a dielectric material spacing apart ends of collinear ones of the first line segments by one or more first distances in a first lateral dimension; and
a plurality of second line segments comprising the conductive material, wherein:
the second line segments are in a same interconnect level as the first line segments and intersect two or more adjacent ones of the first line segments; and
the second line segments have end-to-end lengths in a second lateral dimension, orthogonal to the first lateral dimension, that are a first integer multiple of the line width summed with a second integer multiple of the space width.

10. The IC device of claim 9 , wherein the first integer is at least two, and the second integer is at least one.

11. The IC device of claim 9 , wherein the dielectric material separates adjacent ones of the first line segments in the first lateral dimension by a third integer multiple of the space width summed with a fourth integer multiple of the line width, and wherein the fourth integer is one less than the third integer.

12. The IC device of claim 11 , wherein the first integer is equal to the third integer and the second integer is equal to the fourth integer.

13. A method of fabricating an integrated circuit (IC) device, comprising:
receiving a workpiece with a plurality of material line segments having a line width and separated by a surrounding material occupying a space width between the material line segments;
patterning a first opening and a second opening in a mask layer over the workpiece, wherein the first opening has a smaller lateral dimension than the second opening;
depositing a thin film material over sidewalls of the first opening and second opening, the thin film material reducing the lateral dimension of the second opening and completely occluding the first opening to form a plug mask;
removing at least one of the material line segments exposed by the second opening;
forming a trench pattern within a dielectric material of the workpiece by transferring into the dielectric material a union of a remainder of the material line segments and the plug mask; and
forming interconnect lines by at least partially backfilling the dielectric material with conductive material.

14. The method of claim 13 , wherein removing at least one of the material line segments removes only one of the line segments selectively to the surrounding material.

15. The method of claim 14 , wherein forming the trench pattern further comprises removing the surrounding material selectively from the material line segments, the plug mask protecting a portion of the surrounding material between at least two adjacent ones of the material line segments.

16. The method of claim 13 , wherein the first opening has a minimum lateral width no larger than twice the thickness of the thin film material.

17. The method of claim 16 , wherein the first opening has a minimum lateral width larger than the space width.

18. The method of claim 13 , wherein the conductive material comprises Cu.

19. The method of claim 13 , wherein the interconnect lines comprise first interconnect line segments having a lateral dimension that is approximately equal to the line width.

20. The method of claim 19 , wherein the interconnect lines comprise second line segments intersecting two or more adjacent ones of the first line segments, and wherein the second line segments have a lateral dimension that is at least twice the line width summed with the space width.

Assignees

• Intel Corp

Inventors

• Lin Kevin
• Jezewski Christopher J

Classifications

• H10P50/73

  using masks for insulating materials · CPC title

• H10W20/435 Primary

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10W20/089 Primary

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title

• H01L21/76816 Primary

  Electricity · mapped topic

• H01L21/31144

  Electricity · mapped topic