Tessellation method using recursive sub-division of triangles

Patent metadata

Field	Value
Publication number	US-11830143-B2
Application number	US-202217844424-A
Country	US
Kind code	B2
Filing date	Jun 20, 2022
Priority date	Jun 5, 2015
Publication date	Nov 28, 2023
Grant date	Nov 28, 2023

Abstract

A tessellation method uses tessellation factors defined for each vertex of a patch which may be a quad, a triangle or an isoline. The method is implemented in a computer graphics system and involves comparing the vertex tessellation factors to a threshold. If the vertex tessellation factors for either a left vertex or a right vertex, which define an edge of an initial patch, exceed the threshold, the edge is sub-divided by the addition of a new vertex which divides the edge into two parts and two new patches are formed. New vertex tessellation factors are calculated for each vertex in each of the newly formed patches, both of which include the newly added vertex. The method is then repeated for each of the newly formed patches until none of the vertex tessellation factors exceed the threshold.

First claim

What is claimed is:

1. A method of performing tessellation of surface patches of objects in a 3-D scene in a computer graphics system, the method comprising:
for an initial patch comprising a left vertex and a right vertex connected by an edge and defined in domain space:
comparing a vertex tessellation factor of the left vertex and a vertex tessellation factor of the right vertex to a threshold value, and
in response to determining that either of the vertex tessellation factors of the left and right vertices exceed the threshold value, dividing the initial patch to form two new patches; and

using the newly formed patches in rendering a scene in the computer graphics system.

2. The method according to claim 1 , further comprising:
repeating the method with each newly formed patch as the initial patch.

3. The method according to claim 2 , wherein repeating the method for each newly formed patch as the initial patch comprises:
repeating the method for each newly formed patch as the initial patch until the vertex tessellation factors of the left and right vertices in each patch do not exceed the threshold value.

4. The method according to claim 1 , wherein dividing the initial patch to form two new patches comprises forming a new vertex that sub-divides the edge.

5. The method according to claim 4 , further comprising calculating a vertex tessellation factor for the new vertex, wherein calculating a vertex tessellation factor for the new vertex comprises:
calculating a mean of the vertex tessellation factors of the left and right vertices; and
setting the vertex tessellation factor for the new vertex equal to the calculated mean.

6. The method according to claim 5 , wherein the mean of the vertex tessellation factors of the left and right vertices is given by:
MEAN(LEFT.TF,RIGHT.TF)=MIN(AVG(LEFT.TF,RIGHT.TF),MIN(LEFT.TF,RIGHT.TF)+INTERVAL)
where: LEFT.TF is the vertex tessellation factor of the left vertex, RIGHT.TF is the vertex tessellation factor of the right vertex, AVG( ) is an arithmetic mean of values within the parentheses, MIN( ) is a minimum of a list of values within the parentheses and INTERVAL is a pre-defined parameter.

7. The method according to claim 1 , further comprising reducing the vertex tessellation factor of each vertex in each of the newly formed patches, wherein reducing the vertex tessellation factor of each vertex in each of the newly formed patches comprises reducing each vertex tessellation factor by a pre-defined parameter, INTERVAL.

8. The method according to claim 1 , wherein the initial patch is an isoline patch defined by two vertices, the left vertex and the right vertex.

9. The method according to claim 1 , wherein the initial patch is a triangle patch and wherein the triangle patch is an ordered set of three vertices: a top vertex, the right vertex and the left vertex.

10. The method according to claim 9 , wherein a patch that is divided is a parent patch for the two newly formed patches and wherein the first new patch is an ordered set of three vertices: a top vertex which is a new vertex added to the parent patch, a right vertex which is the left vertex of the parent patch and a left vertex which is the top vertex of the parent patch and wherein the second new patch is an ordered set of three vertices: a top vertex which is the new vertex added to the parent patch, a right vertex which is the top vertex of the parent patch and a left vertex which is the right vertex of the parent patch.

11. The method according to claim 9 , further comprising:
receiving an input patch;
generating one or more initial patches from the input patch; and
repeating the method for each of the plurality of initial patches.

12. A non-transitory computer readable storage medium having stored thereon computer executable program code that when executed causes at least one processor to perform a method of performing tessellation of surface patches of objects in a 3-D scene by,
for an initial patch comprising a left vertex and a right vertex connected by an edge and defined in domain space:
comparing a vertex tessellation factor of the left vertex and a vertex tessellation factor of the right vertex to a threshold value, and
in response to determining that either of the vertex tessellation factors of the left and right vertices exceed the threshold value, dividing the initial patch to form two new patches; and

using the newly formed patches in rendering a scene in the computer graphics system.

13. A hardware tessellation unit comprising hardware logic configured to, for an initial patch comprising a left vertex and a right vertex connected by an edge and defined in domain space, said initial patch representing part of a surface in a 3-D computer graphics scene:
compare a vertex tessellation factor of the left vertex and a vertex tessellation factor of the right vertex to a threshold value;
in response to determining that either of the vertex tessellation factors of the left and right vertices exceed the threshold value, divide the initial patch to form two new patches; and
output the newly formed patches for use in rendering said 3-D computer graphics scene.

14. The hardware tessellation unit according to claim 13 , wherein the hardware logic is further configured to repeat the method with each newly formed patch as the initial patch.

15. The hardware tessellation unit according to claim 13 , further comprising hardware logic configured to calculate a vertex tessellation factor for a new vertex generated when forming the two new patches, the hardware logic configured to:
calculate a mean of the vertex tessellation factors of the left and right vertices; and
set the vertex tessellation factor for the new vertex equal to the calculated mean.

16. The hardware tessellation unit according to claim 13 , wherein the initial patch is an isoline patch defined by two vertices, the left vertex and the right vertex.

17. The hardware tessellation unit according to claim 13 , wherein the initial patch is a triangle patch and wherein the triangle patch is an ordered set of three vertices: a top vertex, the right vertex and the left vertex.

18. The hardware tessellation unit according to claim 17 , wherein a patch that is divided is a parent patch for the two newly formed patches and wherein the first new patch is an ordered set of three vertices: a top vertex which is a new vertex added to the parent patch, a right vertex which is the left vertex of the parent patch and a left vertex which is the top vertex of the parent patch and wherein the second new patch is an ordered set of three vertices: a top vertex which is the new vertex added to the parent patch, a right vertex which is the top vertex of the parent patch and a left vertex which is the right vertex of the parent patch.

19. The hardware tessellation unit according to claim 17 , further comprising hardware logic configured to:
receive an input patch;
generate one or more initial patches from the input patch; and
repeat the method for each of the plurality of initial patches.

20. A graphics processing unit comprising at least one processor and a hardware tessellation unit as set forth in claim 13 .

Assignees

• Imagination Tech Ltd

Inventors

• Lacey Peter Malcolm
• Fenney Simon

Classifications

• G06T17/20 Primary

  Finite element generation, e.g. wire-frame surface description, {tesselation} · CPC title

• G06T15/005

  General purpose rendering architectures · CPC title

• G06T17/205

  Re-meshing · CPC title