Synchronized data chaining using on-chip cache

Patent metadata

Field	Value
Publication number	US-11830102-B2
Application number	US-202217943047-A
Country	US
Kind code	B2
Filing date	Sep 12, 2022
Priority date	Dec 4, 2017
Publication date	Nov 28, 2023
Grant date	Nov 28, 2023

Abstract

Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for generating, by an image sensor of a computing device, frame data comprising sub-frames of image pixel data. A first resource of the system-on-chip provides the frame data to a second resource of the system-on-chip. The frame data is provided to the second resource using a first data path included in the system-on-chip. The first resource provides a token to the second resource using a second data path included in the system-on-chip. A processor of the system-on-chip, uses the token to synchronize production of sub-frames of image pixel data provided by the first resource to the second resource and to synchronize consumption of the sub-frames of image pixel data received by the second resource from the elastic memory buffer.

First claim

What is claimed is:

1. A system-on-a-chip comprising:
a pair of processing devices including a first processing device and a second processing device;
a system-level cache configured to cache memory requests to a memory by the processing devices;
a data communications network that is configured to carry data between the processing devices, the system-level cache, and the memory;
a token switch network that is configured to carry synchronization data between the processing devices to control data sharing through the system-level cache by the processing devices,
wherein the first processing device is configured to store data in the system-level cache through the data communications network, and to provide a token through the token switch network to the second processing device indicating availability of the data stored in the system-level cache, and
wherein the second processing device is configured to receive the token through the token-switch network and, in response, read the data from the system-level cache through the data communications network without the second processing device reading the data from the memory.

2. The system of claim 1 , wherein the token switch network is a different communications network than the data communications network.

3. The system of claim 1 , wherein the first processing device is an image signal processor, and wherein the second processing device is a processing device that is configured to process data generated by the image signal processor.

4. The system of claim 1 , wherein the first processing device is configured to generate audio data, and wherein the second processing device is configured to process the audio data generated by the first processing device.

5. The system of claim 1 , wherein the first processing device and the second processing device are configured to use a same address walk order.

6. The system of claim 1 , wherein the second processing device is configured to provide, to the first processing device using the token switch network, a token indicating that the data generated by the first processing device has been processed by the second processing device.

7. The system of claim 1 , wherein the data generated by the first processing device and read by the second processing device from the system-level cache comprises sub-frame data that is smaller than an image frame of a camera communicatively coupled to the system-on-a-chip.

8. The system of claim 1 , wherein the token switch network is a bidirectional communications network.

9. A method comprising:
generating, by a first processing device of a system-on-a-chip, data to be processed by a second processing device of the system-on-a-chip;
storing, by the first processing device, the generated data in a system-level cache of the system-on-a-chip using a data communications network of the system-on-a-chip, wherein the system-level cache is configured to cache memory requests to a memory by the first processing device and the second processing device;
providing, by the first processing device to the second processing device using a token switch network of the system-on-a-chip, a token indicating the availability of the data stored in the system-level cache;
receiving, by the second processing device, the token from the first processing device using the token switch network; and
in response, reading, by the second processing device, the data from the system-level cache generated by the first processing device using the data communications network without reading the data from the memory.

10. The method of claim 9 , wherein the token switch network is a different communications network than the data communications network.

11. The method of claim 9 , wherein the first processing device is an image signal processor, and wherein the second processing device is a processing device that is configured to process data generated by the image signal processor.

12. The method of claim 9 , wherein the first processing device generates audio data, and wherein the second processing device is configured to process the audio data generated by the first processing device.

13. The method of claim 9 , wherein the first processing device and the second processing device are configured to use a same address walk order.

14. The method of claim 9 , further comprising providing, by the second processing device using the token switch network to the first processing device, a token indicating that the data generated by the first processing device has been processed by the second processing device.

15. The method of claim 9 , wherein the data generated by the first processing device and read by the second processing device from the system-level cache comprises sub-frame data that is smaller than an image frame of a camera communicatively coupled to the system-on-a-chip.

16. The method of claim 9 , wherein the token switch network is a bidirectional communications network.

Assignees

• Google Llc

Inventors

• Dodge Benjamin
• Redgrave Jason Rupert
• Ma Xiaoyu

Classifications

• G06T1/20 Primary

  Processor architectures; Processor configuration, e.g. pipelining · CPC title

• G06F13/28 Primary

  using burst mode transfer, e.g. direct memory access {DMA}, cycle steal (G06F13/32 takes precedence) · CPC title

• G06F15/7825

  Globally asynchronous, locally synchronous, e.g. network on chip · CPC title

• G06T1/60

  Memory management · CPC title

• G06F15/7807

  System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package · CPC title