Memory control method, memory storage device, and memory control circuit unit

Patent metadata

Field	Value
Publication number	US-11829644-B2
Application number	US-202217581858-A
Country	US
Kind code	B2
Filing date	Jan 22, 2022
Priority date	Dec 8, 2021
Publication date	Nov 28, 2023
Grant date	Nov 28, 2023

Abstract

A memory control method, a memory storage device, and a memory control circuit unit are provided. The memory control method includes: receiving a read command from a host system; in response to a first physical erasing unit being a first type physical unit, sending a first operation command sequence to instruct a rewritable non-volatile memory module to read a first physical programming unit based on a first electronic configuration; and in response to the first physical erasing unit being a second type physical unit, sending a second operation command sequence to instruct the rewritable non-volatile memory module to read the first physical programming unit based on a second electronic configuration. The first electronic configuration is different from the second electronic configuration.

First claim

What is claimed is:

1. A memory control method for a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module comprises a plurality of physical erasing units, the memory control method comprising:
receiving a read command from a host system, wherein the read command instructs to read a first logical unit, the first logical unit is mapped to a first physical programming unit, and the first physical programming unit belongs to a first physical erasing unit among the physical erasing units;
in response to the first physical erasing unit being a first type physical unit, sending a first operation command sequence to instruct the rewritable non-volatile memory module to read the first physical programming unit based on a first electronic configuration; and
in response to the first physical erasing unit being a second type physical unit, sending a second operation command sequence to instruct the rewritable non-volatile memory module to read the first physical programming unit based on a second electronic configuration, wherein
the first electronic configuration is different from the second electronic configuration, and
a first total number of physical programming units in an erased status in the first type physical unit is different from a second total number of physical programming units in the erased status in the second type physical unit,
according to a total number of physical programming units in the erased status in the first physical erasing unit, judging that the first physical erasing unit is the first type physical unit or the second type physical unit.

2. The memory control method according to claim 1 , wherein the first total number is not zero, and the second total number is zero.

3. The memory control method according to claim 1 , wherein the step of according to the total number of the physical programming units in the erased status in the first physical erasing unit, judging that the first physical erasing unit is the first type physical unit or the second type physical unit comprises:
in response to the total number of the physical programming units in the erased status in the first physical erasing unit not being zero, judging that the first physical erasing unit is the first type physical unit; and
in response to the total number of the physical programming units in the erased status in the first physical erasing unit being zero, judging that the first physical erasing unit is the second type physical unit.

4. The memory control method according to claim 1 , wherein the first electronic configuration comprises a first read voltage level, and the first operation command sequence instructs the rewritable non-volatile memory module to use the first read voltage level to read the first physical programming unit,
the second electronic configuration comprises a second read voltage level, and the second operation command sequence instructs the rewritable non-volatile memory module to use the second read voltage level to read the first physical programming unit, and
the first read voltage level is different from the second read voltage level.

5. The memory control method according to claim 4 , further comprising:
according to a distribution of physical programming units in a programmed status in the first physical erasing unit, determining the first read voltage level.

6. The memory control method according to claim 5 , further comprising:
according to the first read voltage level, determining a read voltage level for reading a remaining physical programming unit in the first physical erasing unit.

7. The memory control method according to claim 1 , wherein the first electronic configuration comprises a turn-on voltage applied to a second physical programming unit in the first physical erasing unit, and the first operation command sequence instructs the rewritable non-volatile memory module to adjust the turn-on voltage, and
the second physical programming unit is not in the programmed status.

8. The memory control method according to claim 7 , wherein the second physical programming unit comprises a plurality of memory cells, and
the turn-on voltage is applied to control gates of the memory cells.

9. The memory control method according to claim 1 , wherein the first electronic configuration comprises a bit line voltage applied to the first physical erasing unit, and the first operation command sequence instructs the rewritable non-volatile memory module to adjust the bit line voltage.

10. The memory control method according to claim 9 , wherein the first physical erasing unit comprises a plurality of memory cells and at least one word line,
the memory cells are coupled to the at least one word line, and
the bit line voltage is applied to the at least one word line.

11. A memory storage device, comprising:
a connection interface unit, used to couple to a host system;
a rewritable non-volatile memory module, comprising a plurality of physical erasing units; and
a memory control circuit unit, coupled to the connection interface unit and the rewritable non-volatile memory module, wherein
the memory control circuit unit is used to:
receive a read command from the host system, wherein the read command instructs to read a first logical unit, the first logical unit is mapped to a first physical programming unit, and the first physical programming unit belongs to a first physical erasing unit among the physical erasing units;
in response to the first physical erasing unit being a first type physical unit, send a first operation command sequence to instruct the rewritable non-volatile memory module to read the first physical programming unit based on a first electronic configuration; and
in response to the first physical erasing unit being a second type physical unit, send a second operation command sequence to instruct the rewritable non-volatile memory module to read the first physical programming unit based on a second electronic configuration, wherein
the first electronic configuration is different from the second electronic configuration, and
a first total number of physical programming units in an erased status in the first type physical unit is different from a second total number of physical programming units in the erased status in the second type physical unit,
wherein the memory control circuit unit is further used to:

according to a total number of physical programming units in the erased status in the first physical erasing unit, judge that the first physical erasing unit is the first type physical unit or the second type physical unit.

12. The memory storage device according to claim 11 , wherein the first total number is not zero, and the second total number is zero.

13. The memory storage device according to claim 11 , wherein the operation of according to the total number of the physical programming units in the erased status in the first physical erasing unit, judging that the first physical erasing unit is the first type physical unit or the second type physical unit comprises:
in response to the total number of the physical programming units in the erased status in the first physical erasing unit not being zero, judging that the first physical erasing unit is the first type physical unit; and
in response to the total number of the physical programming units in the erased status in the first physical erasing unit being zero, judging that the first physical erasing unit is the second type physical unit.

14. The memory storage device according to claim 11 , wherein the first electronic configuration comprises a first read voltage level, and the first op

Assignees

• Phison Electronics Corp

Inventors

• Su Po-Cheng
• Wang Chih-Wei
• Hsu Yu-Cheng
• Lin Wei

Classifications

• G06F3/0659 Primary

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title

• G06F3/0619 Primary

  in relation to data integrity, e.g. data losses, bit errors · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G06F11/10

  Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's · CPC title