Device and method for flexibly summing matrix values

Patent metadata

Field	Value
Publication number	US-11829441-B2
Application number	US-202217834203-A
Country	US
Kind code	B2
Filing date	Jun 7, 2022
Priority date	May 7, 2020
Publication date	Nov 28, 2023
Grant date	Nov 28, 2023

Abstract

A device includes a matrix transpose component, a matrix processing component, a data alignment component, and a data reduction component. The matrix transpose component is configured to transpose an input matrix of elements to output an output matrix of the elements that have been transposed. The matrix processing component is configured to multiply a first multiplication input matrix with a second multiplication input matrix, wherein the output matrix of the matrix transpose component is utilized as the first multiplication input matrix and a mask vector is utilized as the second multiplication input matrix. The data alignment component is configured to modify at least a portion of elements of a result of the matrix processing component. The data reduction component is configured to sum at least the elements of the modified result of the matrix processing component to determine a sum of the group of values.

First claim

What is claimed is:

1. A system, comprising:
one or more integrated circuit processors including:
a matrix transpose component configured to transpose an initial matrix of elements to output an output matrix of the elements that have been transposed;
a matrix processing component configured to multiply the output matrix with a mask vector of elements to determine a result vector;
a data modification component configured to modify at least a portion of elements of the result vector to determine a modified vector of elements; and
a data reduction component configured to sum the elements of the modified vector of elements; and

a memory storing at least the elements of the initial matrix of elements.

2. The system of claim 1 , wherein the initial matrix represents, in an alternative format, an input matrix of values.

3. The system of claim 2 , wherein at least one element of the initial matrix is represented using a first number of bits.

4. The system of claim 3 , wherein at least one value of the input matrix is represented using a second number of bits greater than the first number of bits.

5. The system of claim 3 , wherein at least one element of the mask vector is a value of one as represented using the first number of bits.

6. The system of claim 1 , wherein the matrix processing component is configured to multiply the output matrix with the mask vector to determine the result vector including by being configured to compute a dot product of a row of the output matrix with the mask vector.

7. The system of claim 1 , wherein the data modification component is configured to modify at least the portion of elements of the result vector to determine the modified vector of elements including by being configured to bit shift, by a specified bit shift amount, at least one element of at least the portion of elements of the result vector.

8. The system of claim 7 , wherein the specified bit shift amount is twenty-four bits, sixteen bits, eight bits, or zero bits.

9. The system of claim 1 , wherein the matrix transpose component is configured to transpose the initial matrix of elements to output the output matrix including by being configured to copy elements of the initial matrix to a buffer storage.

10. A method, comprising:
using a matrix transpose component of one or more integrated circuit processors to transpose an initial matrix of elements to output an output matrix of the elements that have been transposed;
using a matrix processing component of the one or more integrated circuit processors to multiply the output matrix with a mask vector of elements to determine a result vector;
using a data modification component of the one or more integrated circuit processors to modify at least a portion of elements of the result vector to determine a modified vector of elements; and
using a data reduction component of the one or more integrated circuit processors to sum the elements of the modified vector of elements.

11. The method of claim 10 , wherein the initial matrix represents, in an alternative format, an input matrix of values.

12. The method of claim 11 , wherein at least one element of the initial matrix is represented using a first number of bits.

13. The method of claim 12 , wherein at least one value of the input matrix is represented using a second number of bits greater than the first number of bits.

14. The method of claim 11 , further comprising storing the values of the input matrix in a first location of a memory using a specified amount of storage space.

15. The method of claim 14 , further comprising storing the elements of the initial matrix in a second location of the memory using the specified amount of storage.

16. The method of claim 11 , wherein the input matrix is utilized in an artificial neural network operation.

17. The method of claim 12 , wherein at least one element of the mask vector is a value of one as represented using the first number of bits.

18. The method of claim 10 , wherein using the data modification component of the one or more integrated circuit processors to modify at least the portion of elements of the result vector includes using the one or more integrated circuit processors to bit shift, by a specified bit shift amount, at least one element of at least the portion of elements of the result vector.

19. The method of claim 18 , wherein the specified bit shift amount is a multiple of eight bits.

20. A system, comprising:
one or more integrated circuit processors including:
a matrix transpose component configured to transpose an initial matrix of elements to output an output matrix of the elements that have been transposed;
a matrix processing component configured to multiply the output matrix with a mask vector of elements to determine a result vector;
a data modification component configured to modify at least a portion of elements of the result vector to determine a modified vector of elements; and
a data reduction component configured to sum the elements of the modified vector of elements; and

a memory comprising a first portion configured to store the elements of the initial matrix of elements and a second portion configured to store the output matrix.

Assignees

• Meta Platforms Inc

Inventors

• Nair Krishnakumar Narayanan
• Ulrich Thomas Mark
• Khish Ardestani Zadeh Ehsan

Classifications

• G06F17/16 Primary

  Matrix or vector computation {, e.g. matrix-matrix or matrix-vector multiplication, matrix factorization (matrix transposition G06F7/78)} · CPC title

• G06F7/78

  for changing the order of data flow, e.g. matrix transposition or LIFO buffers; Overflow or underflow handling therefor · CPC title

• G06F17/15

  Correlation function computation {including computation of convolution operations (arithmetic circuits for sum of products per se, e.g. multiply-accumulators G06F7/5443; digital filters, e.g. FIR, IIR, adaptive filters H03H17/00)} · CPC title

• G06N3/063

  using electronic means · CPC title

• G06F7/5443

  Sum of products (for applications thereof, see the relevant places, e.g. G06F17/10, H03H17/00) · CPC title