Superconducting circuit including superconducting qubits

Patent metadata

Field	Value
Publication number	US-11825752-B2
Application number	US-202217937160-A
Country	US
Kind code	B2
Filing date	Sep 30, 2022
Priority date	Jun 6, 2019
Publication date	Nov 21, 2023
Grant date	Nov 21, 2023

Abstract

The present disclosure discloses a device and a method for fabricating a superconducting circuit including a superconducting qubit. The superconducting circuit comprises a bottom electrode interconnecting a superconducting qubit and a first part of the superconducting circuit. The bottom electrode comprises a bottom electrode of the superconducting qubit and a bottom electrode of the first part of the superconducting circuit. The bottom electrode of the superconducting qubit and the bottom electrode of the first part of the superconducting circuit are formed in a first superconducting layer.

First claim

The invention claimed is:

1. A method for preparing a superconducting circuit, comprising:
covering a first area with a first photoresist and covering a second area with a second photoresist, wherein the first area comprises an area where a bottom electrode of a superconducting qubit of the superconducting circuit is located, the second area comprises an area where a bottom electrode of a first part of the superconducting circuit is located, and the second photoresist covers the first photoresist;
performing lithography on the second photoresist to form the bottom electrode of the first part of the superconducting circuit, and to expose the first photoresist covered by the second photoresist;
performing lithography on the exposed first photoresist to form the bottom electrode of the superconducting qubit;
depositing first superconducting material on the first area and the second area; and
removing the first photoresist and the second photoresist to obtain a bottom electrode of the superconducting circuit, wherein the bottom electrode includes the bottom electrode of the superconducting qubit and the bottom electrode of the first part of the superconducting circuit that are formed in a first superconducting layer formed by the deposited first superconducting material.

2. The method according to claim 1 , wherein the bottom electrode of the first part of the superconducting circuit is integrally formed with the bottom electrode of the superconducting circuit.

3. The method according to claim 1 , wherein:
the bottom electrode of the superconducting qubit is formed through lithography performed on the exposed first photoresist using at least one of the following manners: overlap technique or shadow evaporation technique;
the bottom part of the first part of the superconducting circuit is formed through lithograph performed on the second photoresist using at least one of the following manners: lift-off technique, wet etching technique, or dry etching technique; and
the first photoresist comprises an e-beam lithography photoresist, and the second photoresist comprises an optical photoresist.

4. The method according to claim 1 , further comprising:
covering a third area with a third photoresist and covering a fourth area with a fourth photoresist based on the bottom electrode of the superconducting circuit, wherein the third area comprises an area where a top electrode of the superconducting qubit of the superconducting circuit is located, the fourth area comprises an area where a top electrode of the second part of the superconducting circuit is located, and the fourth photoresist covers the third photoresist;
performing lithography on the fourth photoresist to form the top electrode of the second part of the superconducting circuit, and to expose the third photoresist covered by the fourth photoresist;
performing lithography on the exposed third photoresist to form the top electrode of the superconducting qubit;
preparing an insulation layer at an overlapped area between the top electrode and the bottom electrode of the superconducting qubit;
depositing second superconducting material on the third area and the fourth area; and
removing the third photoresist and the fourth photoresist to obtain a top electrode of the superconducting circuit, wherein the top electrode includes the top electrode of the superconducting qubit and the top electrode of the second part of the superconducting circuit that are formed in a second superconducting layer formed by the deposited second superconducting material.

5. The method according to claim 4 , wherein
the top electrode of the superconducting qubit is formed through lithography performed on the exposed third photoresist using at least one of the following manners: overlap technique or shadow evaporation technique;
the top electrode of the second part of the superconducting circuit is formed through lithography performed on the fourth photoresist using at least one of the following manners: lift-off technique, wet etching technique, or dry etching technique; and
the third photoresist comprises an e-beam lithography photoresist, and the fourth photoresist comprises an optical photoresist.

6. The method according to claim 4 , wherein the first superconducting material or the second superconducting material comprises at least one of the following: aluminum, niobium, niobium nitride, or titanium nitride.

Assignees

• Alibaba Group Holding Ltd

Inventors

• Deng Hao

Classifications

• G06N10/40

  Physical realisations or architectures of quantum processors or components for manipulating qubits, e.g. qubit coupling or qubit control · CPC title

• H10N60/805 Primary

  for Josephson-effect devices · CPC title

• H10N60/0912

  of Josephson-effect devices · CPC title

• H10N60/12

  Josephson-effect devices · CPC title

• H10N60/82 Primary

  Current path · CPC title