Protocol independent programmable switch (PIPS) for software defined data center networks

Patent metadata

Field	Value
Publication number	US-11824796-B2
Application number	US-202016992978-A
Country	US
Kind code	B2
Filing date	Aug 13, 2020
Priority date	Dec 30, 2013
Publication date	Nov 21, 2023
Grant date	Nov 21, 2023

Abstract

A software-defined network (SDN) system, device and method comprise one or more input ports, a programmable parser, a plurality of programmable lookup and decision engines (LDEs), programmable lookup memories, programmable counters, a programmable rewrite block and one or more output ports. The programmability of the parser, LDEs, lookup memories, counters and rewrite block enable a user to customize each microchip within the system to particular packet environments, data analysis needs, packet processing functions, and other functions as desired. Further, the same microchip is able to be reprogrammed for other purposes and/or optimizations dynamically.

First claim

What is claimed is:

1. A method of operating a switch microchip for a software-defined network, the method comprising:
parsing packet context data from headers of a plurality of incoming packets with a programmable parser based on a software-defined parse graph of the parser including a plurality of paths; and
transmitting one or more data lookup requests to and receiving processing data based on the requests from dynamically reconfigurable lookup memories with the lookup and decision engines, wherein the lookup memories are configured as a logical overlay such that the scaling and width of a portion of the lookup memories allocated to each of the paths is software-defined by the user.

2. The method of claim 1 , wherein starting from the same initial node of the parse graph, each path through the parse graph represents a combination of layer types of one of the headers that is able to be recognized by the parser.

3. The method of claim 2 , wherein portions of the paths overlap.

4. The method of claim 1 , further comprising expanding each layer of each of the headers parsed by the parser with a rewrite block to form a expanded layer type of a generic size based on a protocol associated with the layer.

5. The method of claim 4 , wherein the rewrite block generates a bit vector that indicates which portions of the expanded layer type contain valid data and which portions of the expanded layer type contain data added during the expanding by the rewrite block.

6. The method of claim 1 , wherein the tables of the lookup memories are each able to be independently set in hash, direct access or longest prefix match operational modes.

7. The method of claim 6 , wherein the tables of the lookup memories are able to be dynamically reformatted and reconfigured by the user such that a number of tiles of the lookup memories partitioned and allocated for lookup paths coupled to the lookup memories is based on memory capacity needed by each of the lookup paths.

8. The method of claim 1 , wherein the transmitting is by at least one lookup and decision engine including:
a Key Generator configured to generate a set of lookup keys for each input token; and
an Output Generator configured to generate an output token by modifying the input token based on content of lookup results associated with the set of lookup keys.

9. The method of claim 1 , further comprising performing counting operations with a counter block that comprises:
N wrap-around counters, wherein each of the N wrap-around counters is associated with a counter identification; and
an overflow FIFO used and shared by the N wrap-around counters, wherein the overflow FIFO stores the associated counter identifications of all counters that are overflowing.

10. A method of operating a switch microchip for a software-defined network, the method comprising:
parsing packet context data from headers of a plurality of incoming packets with a programmable parser based on a software-defined parse graph of the parser including a plurality of paths; and
transmitting one or more data lookup requests to and receiving processing data based on the requests from dynamically reconfigurable lookup memories with the lookup and decision engines, wherein the lookup memories are configured as a logical overlay such that the scaling and width of a portion of the lookup memories allocated to each of the paths is software-defined by the user, wherein each of the lookup and decision engines comprise:
an Input Buffer for temporarily storing input tokens before input tokens are processed by the lookup and decision engine;
a Profile Table for identifying positions of fields in each of the input tokens;
a Lookup Result Merger for joining the input token with the lookup result and for sending the joined input token with the lookup result to the Output Generator;
a Loopback Checker for determining whether the output token should be sent back to the current lookup and decision engine or to another lookup and decision engine; and
a Loopback Buffer for storing loopback tokens.

11. The method of claim 10 , wherein Control Paths of both the Key Generator and the Output Generator are programmable such that users are able to configure the lookup and decision engine to support different network features and protocols.

Assignees

• Marvell Asia Pte Ltd

Inventors

• Hutchison Guy Townsend
• Gandhi Sachin Ramesh
• Daniel Tsahi
• Schmidt Gerald
• Fishman Albert
• White Martin Leslie
• Shah Zubin

Classifications

• H04L45/745

  Address table lookup; Address filtering · CPC title

• H04L45/7452

  Multiple parallel or consecutive lookup operations (lookup operation involving Bloom filters H04L45/7459) · CPC title

• H04L49/109 Primary

  Integrated on microchip, e.g. switch-on-chip · CPC title

• H04L45/64 Primary

  using an overlay routing layer · CPC title

• G06F3/0604

  Improving or facilitating administration, e.g. storage management · CPC title