Automatic protection against runt pulses

Patent metadata

Field	Value
Publication number	US-11824536-B2
Application number	US-202318112812-A
Country	US
Kind code	B2
Filing date	Feb 22, 2023
Priority date	Mar 18, 2021
Publication date	Nov 21, 2023
Grant date	Nov 21, 2023

Abstract

An apparatus includes an adjustment circuit configured to receive a pulsed-width modulation (PWM) input, generate an adjusted PWM signal based upon the PWM input, and determine that a first pulse of the PWM input is shorter than a runt signal limit. The adjustment circuit is further configured to, in the adjusted PWM signal, extend the first pulse of the PWM input based on the determination that the PWM input is shorter than the runt signal limit, and output the adjusted PWM signal to an electronic device.

First claim

What is claimed is:

1. An apparatus, comprising:
an adjustment circuit to:
receive a pulsed-width modulation (PWM) input;
generate an adjusted PWM signal based upon the PWM input;
determine that a first pulse of the PWM input is shorter than a runt signal limit;
in the adjusted PWM signal, extend the first pulse of the PWM input based on the determination that the PWM input is shorter than the runt signal limit; and
output the adjusted PWM signal to an electronic device; and

a counter to begin a determination of a length of the first pulse of the PWM input after a prescribed delay between the PWM input and the output of the adjusted PWM signal.

2. An apparatus, comprising:
an adjustment circuit to:
receive a pulsed-width modulation (PWM) input, the PWM input to include a PWML signal and a PWMH signal;
generate an adjusted PWM signal based upon the PWM input, the adjusted PWM signal to include an adjusted PWML signal and an adjusted PWMH signal, the PWMH signal and the PWML signal to include PWM signals and to be complements of each other during a plurality of clock cycles, the adjusted PWMH signal and the adjusted PWML signal to include PWM signals and to be complements of each other during a plurality of clock cycles;
determine that a first pulse of the PWM input is shorter than a runt signal limit;
in the adjusted PWM signal, extend the first pulse of the PWM input based on the determination that the PWM input is shorter than the runt signal limit;
selectively adjust the PWMH signal to generate the adjusted PWMH signal and selectively adjust the PWML signal to generate the adjusted PWML signal; and
output the adjusted PWM signal to an electronic device; and

a counter to:
continuously determine lengths of respective pulses of the PWMH signal or the PWML signal; and
begin determination of a length of a respective pulse of one the PWMH signal or the PWML signal after a changed edge on the PWMH signal or the PWML signal and after a changed edge on the adjusted PWMH signal or on the adjusted PWML signal since a last reset of the counter.

3. The apparatus of claim 2 , wherein:
the first pulse and a second pulse are of the PWMH signal;
the adjustment circuit is further to, based upon extension of the first pulse, shorten the second pulse to generate the adjusted PWMH signal, the second pulse immediately following the first pulse;
the PWML signal includes a third pulse and a fourth pulse, the third pulse a complement of the first pulse, the fourth pulse a complement of the second pulse;
the adjustment circuit is to:
determine that the third pulse is a runt pulse;
extend the third pulse based upon the determination that third pulse is a runt pulse and, based upon extension of third pulse, shorten the fourth pulse to generate the adjusted PWML signal.

4. A method, comprising:
receiving a pulsed-width modulation (PWM) input;
generating an adjusted PWM signal based upon the PWM input;
determining that a first pulse of the PWM input is shorter than a runt signal limit;
with a counter, beginning a determination of a length of the first pulse of the PWM input after a prescribed delay between the PWM input and the output of the adjusted PWM signal;
in the adjusted PWM signal, extending the first pulse of the PWM input based on the determination that the PWM input is shorter than the runt signal limit; and
outputting the adjusted PWM signal to an electronic device.

5. A method, comprising:
receiving a pulsed-width modulation (PWM) input, the PWM input to include a PWML signal and a PWMH signal;
generating an adjusted PWM signal based upon the PWM input, the adjusted PWM signal to include an adjusted PWML signal and an adjusted PWMH signal, the PWMH signal and the PWML signal to include PWM signals and to be complements of each other during a plurality of clock cycles, the adjusted PWMH signal and the adjusted PWML signal to include PWM signals and to be complements of each other during a plurality of clock cycles;
determining that a first pulse of the PWM input is shorter than a runt signal limit;
in the adjusted PWM signal, extending the first pulse of the PWM input based on the determination that the PWM input is shorter than the runt signal limit;
selectively adjusting the PWMH signal to generate the adjusted PWMH signal and selectively adjust the PWML signal to generate the adjusted PWML signal;
with a counter:
continuously determining lengths of respective pulses of the PWMH signal; and
beginning determination of a length of a respective pulse of one the PWMH signal or the PWML signal after a changed edge on the PWMH signal or the PWML signal and after a changed edge on the adjusted PWMH signal or on the adjusted PWML signal since a last reset of the counter; and

outputting the adjusted PWM signal to an electronic device.

6. The method of claim 5 , wherein:
the first pulse and a second pulse are of the PWMH signal;
the PWML signal includes a third pulse and a fourth pulse, the third pulse a complement of the first pulse, the fourth pulse a complement of the second pulse; and
the method includes:
based upon extension of the first pulse, shortening the second pulse to generate the adjusted PWMH signal, the second pulse immediately following the first pulse;
determining that the third pulse is a runt pulse; and
extending the third pulse based upon the determination that third pulse is a runt pulse and, based upon extension of third pulse, shortening the fourth pulse to generate the adjusted PWML signal.

7. A microcontroller, comprising:
a pulsed-width modulation (PWM) generation circuit to generate a PWM input;
an adjustment circuit to:
receive the PWM input;
generate an adjusted PWM signal based upon the PWM input;
determine that a first pulse of the PWM input is shorter than a runt signal limit;
in the adjusted PWM signal, extend the first pulse of the PWM input based on the determination that the PWM input is shorter than the runt signal limit; and
output the adjusted PWM signal to an electronic device; and

a counter to begin a determination of a length of the first pulse of the PWM input after a prescribed delay between the PWM input and the output of the adjusted PWM signal.

8. A microcontroller, comprising:
a pulsed-width modulation (PWM) generation circuit to generate a PWM input;
an adjustment circuit to:
receive the PWM input, the PWM input to include a PWML signal and a PWMH signal;
generate an adjusted PWM signal based upon the PWM input, the adjusted PWM signal to include an adjusted PWML signal and an adjusted PWMH signal, the PWMH signal and the PWML signal to include PWM signals and to be complements of each other during a plurality of clock cycles, the adjusted PWMH signal and the adjusted PWML signal to include PWM signals and to be complements of each other during a plurality of clock cycles;
determine that a first pulse of the PWM input is shorter than a runt signal limit;
in the adjusted PWM signal, extend the first pulse of the PWM input based on the determination that the PWM input is shorter than the runt signal limit;
selectively adjust the PWMH signal to generate the adjusted PWMH signal and selectively adjust the PWML signal to generate the adjusted PWML signal; and
output the adjusted PWM signal to an electronic device; and

a counter to:
continuously determine lengths of respective pulses of the PWMH signal or the PWML signal; and
begin determination of a length of a respective pulse of one the PWMH signal or the PWML signal after a changed edge on the PWMH signal or the PWML signal and after a changed edge on the adjusted PWMH signal or on the adjusted PWML signal since a last reset of the counter.

9. The microcontroller

Assignees

• Microchip Tech Inc

Inventors

• Yuenyongsgool Yong
• Bowling Stephen
• Ovalle Pedro

Classifications

• H03K3/017 Primary

  Adjustment of width or dutycycle of pulses (pulse width modulation H03K7/08 {; to maintain energy constant H03K3/015}) · CPC title

• G06F1/06

  Clock generators producing several clock signals {(G06F1/08 - G06F1/14 take precedence)} · CPC title

• H03K21/02

  Input circuits · CPC title

• H03K17/162 Primary

  without feedback from the output circuit to the control circuit · CPC title

• H03K5/04

  by increasing duration; by decreasing duration · CPC title