Transmit driver architecture with a jtag configuration mode, extended equalization range, and multiple power supply domains

Patent metadata

Field	Value
Publication number	US-11824534-B2
Application number	US-202117455195-A
Country	US
Kind code	B2
Filing date	Nov 16, 2021
Priority date	Nov 16, 2021
Publication date	Nov 21, 2023
Grant date	Nov 21, 2023

Abstract

A transmit driver architecture with a test mode (e.g., a JTAG configuration mode), extended equalization range, and/or multiple power supply domains. One example transmit driver circuit generally includes one or more driver unit cells having a differential input node pair configured to receive an input data signal and having a differential output node pair configured to output an output data signal; a plurality of power switches coupled between the differential output node pair and one or more power supply rails; a first set of one or more drivers coupled between a first test node of a differential test data path and a first output node of the differential output node pair; and a second set of one or more drivers coupled between a second test node of the differential test data path and a second output node of the differential output node pair.

First claim

What is claimed is:

1. A transmit driver circuit comprising:
one or more driver unit cells having a differential input node pair configured to receive an input data signal and having a differential output node pair configured to output an output data signal;
a plurality of power switches coupled between the differential output node pair and one or more power supply rails;
a first set of one or more drivers coupled between a first test node of a differential test data path and a first output node of the differential output node pair; and
a second set of one or more drivers coupled between a second test node of the differential test data path and a second output node of the differential output node pair.

2. The transmit driver circuit of claim 1 , wherein the differential test data path comprises a Joint Test Action Group (JTAG) data path.

3. The transmit driver circuit of claim 1 , wherein the one or more driver unit cells and the plurality of power switches are configured to be powered off during a test mode for the transmit driver circuit, such that the transmit driver circuit is configured to function as a voltage-mode driver during the test mode.

4. The transmit driver circuit of claim 1 , further comprising:
a first set of one or more resistive elements coupled between an output of the first set of one or more drivers and the first output node of the differential output node pair; and
a second set of one or more resistive elements coupled between an output of the second set of one or more drivers and the second output node of the differential output node pair.

5. The transmit driver circuit of claim 4 , wherein at least one of the first set or the second set of one or more resistive elements comprises a switched array of resistive elements.

6. The transmit driver circuit of claim 1 , wherein the plurality of power switches comprises:
a first switch coupled between a first power supply rail of the one or more power supply rails and the first output node of the differential output node pair;
a second switch coupled between a second power supply rail of the one or more power supply rails and the first output node of the differential output node pair, wherein the first power supply rail has a first voltage different from a second voltage of the second power supply rail;
a third switch coupled between the first power supply rail and the second output node of the differential output node pair; and
a fourth switch coupled between the second power supply rail and the second output node of the differential output node pair.

7. The transmit driver circuit of claim 1 , wherein the first and second sets of one or more drivers each comprise a plurality of inverters coupled in series.

8. The transmit driver circuit of claim 1 , further comprising a control module configured to generate the input data signal based on two main cursors, one postcursor, and three precursors for equalization.

9. The transmit driver circuit of claim 8 , wherein the control module is configured to program one of the precursors to function as one of the main cursors with a lower cursor weightage than a nominal cursor weightage for the one of the main cursors.

10. The transmit driver circuit of claim 8 , wherein the control module is configured to program the postcursor to function as one of the main cursors with a lower cursor weightage than a nominal cursor weightage for the one of the main cursors.

11. The transmit driver circuit of claim 8 , wherein the control module is configured to program a first one of the main cursors to function as one of the precursors with a higher cursor weightage than a nominal cursor weightage for the one of the precursors.

12. The transmit driver circuit of claim 11 , wherein the control module is configured to program a second one of the main cursors to function as the postcursor with a higher cursor weightage than a nominal cursor weightage for the postcursor.

13. A programmable integrated circuit (IC) comprising a serial/deserializer, wherein the serial/deserializer comprises the transmit driver circuit of claim 1 .

14. A method of driving data, comprising:
receiving an input data signal at a differential input node pair of a driver unit cell of a transmit driver circuit;
generating an output data signal using the driver unit cell; and
outputting the output data signal at a differential output node pair of the transmit driver circuit, wherein the transmit driver circuit comprises:
a plurality of power switches coupled between the differential output node pair and one or more power supply rails;
a first set of one or more drivers coupled between a first test node of a differential test data path and a first output node of the differential output node pair; and
a second set of one or more drivers coupled between a second test node of the differential test data path and a second output node of the differential output node pair.

15. The method of claim 14 , further comprising:
powering off the driver unit cell and the plurality of power switches;
receiving an input test signal at the differential test data path;
driving the input test signal with the first and second sets of one or more drivers; and
outputting an output test signal at the differential output node pair while the driver unit cell and the plurality of power switches are powered off.

16. The method of claim 15 , wherein the input test signal comprises a Joint Test Action Group (JTAG) signal.

17. The method of claim 14 , wherein the plurality of power switches comprises:
a first switch coupled between a first power supply rail of the one or more power supply rails and the first output node of the differential output node pair;
a second switch coupled between a second power supply rail of the one or more power supply rails and the first output node of the differential output node pair, wherein the first power supply rail has a first voltage different from a second voltage of the second power supply rail;
a third switch coupled between the first power supply rail and the second output node of the differential output node pair; and
a fourth switch coupled between the second power supply rail and the second output node of the differential output node pair.

18. The method of claim 17 , wherein generating the output data signal comprises:
powering the transmit driver circuit with the first and third switches closed and with the second and fourth switches open; and
based on a swing condition of the transmit driver circuit, changing to powering the transmit driver circuit with the second and fourth switches closed and with the first and third switches open.

19. The method of claim 14 , further comprising generating the input data signal based on two main cursors, one postcursor, and three precursors for equalization, wherein generating the input data signal comprises at least one of:
programming a first one of the main cursors to function as one of the precursors with a higher cursor weightage than a nominal cursor weightage for the one of the precursors;
programming a second one of the main cursors to function as the postcursor with a higher cursor weightage than a nominal cursor weightage for the postcursor;
programming the one of the precursors to function as the first one of the main cursors with a lower cursor weightage than a nominal cursor weightage for the first one of the main cursors; or
programming the postcursor to function as the second one of the main cursors with a lower cursor weightage than a nominal cursor weightage for the second

Assignees

• Xilinx Inc

Inventors

• Narang Nakul
• Lim Siok Wei
• Chen Luhui
• Wang Yipeng
• Tan Kee Hian

Classifications

• H03K19/17788

  for input/output [I/O] voltages · CPC title

• H04L25/03878

  Line equalisers; line build-out devices · CPC title

• H04L25/0272 Primary

  Arrangements for coupling to multiple lines, e.g. for differential transmission · CPC title

• H03K19/17744 Primary

  for input/output signals · CPC title

• G06F13/102

  where the program performs an interfacing function, e.g. device driver (G06F13/105 takes precedence; contention policies within device drivers G06F9/4881; scheduling within device drivers G06F9/52) · CPC title