Chip package with substrate integrated waveguide and waveguide interface

Patent metadata

Field	Value
Publication number	US-11824019-B2
Application number	US-202117356831-A
Country	US
Kind code	B2
Filing date	Jun 24, 2021
Priority date	Jun 24, 2021
Publication date	Nov 21, 2023
Grant date	Nov 21, 2023

Abstract

A chip package includes a chip configured to generate and/or receive a signal; a laminate substrate including a substrate integrated waveguide (SIW) for carrying the signal, the substrate integrated waveguide including a chip-to-SIW transition structure configured to couple the signal between the SIW and the chip and a SIW-to-waveguide transition structure configured to couple the signal out of the SIW or into the SIW, wherein the SIW-to-waveguide transition structure includes a waveguide aperture; and a plurality of electrical interfaces arranged about a periphery of the waveguide aperture, the plurality of electrical interfaces configured to receive the signal from the SIW-to-waveguide transition structure and output the signal from the chip package or to couple the signal to the SIW-to-waveguide transition structure and into the chip package.

First claim

What is claimed is:

1. A chip package, comprising:
a chip configured to generate a signal;
a laminate substrate comprising a substrate integrated waveguide (SIW) for carrying the signal through the chip package, the SIW comprising:
a chip-to-SIW transition structure configured to couple the signal into the SIW from the chip,
a SIW-to-waveguide transition structure configured to couple the signal out of the SIW, wherein the SIW-to-waveguide transition structure comprises a waveguide aperture,
a first metal layer that extends in a signal propagation direction from the chip-to-SIW transition structure to the SIW-to-waveguide transition structure,
a second metal layer that extends parallel to the first metal layer, and
two rows of vias that extend in the signal propagation direction and encircle the waveguide aperture, wherein each via of the two rows of vias is connected to the first metal layer and the second metal layer; and

a plurality of electrical interfaces arranged about a periphery of the waveguide aperture, the plurality of electrical interfaces configured to receive the signal from the SIW-to-waveguide transition structure and output the signal from the chip package.

2. The chip package of claim 1 , wherein at least one of:
the waveguide aperture extends from the SIW-to-waveguide transition structure though an area defined by the plurality of electrical interfaces, or
the chip is a radar monolithic microwave integrated circuit (MIMIC) and the signal is a radar signal.

3. The chip package of claim 1 , wherein chip is a radio frequency (RF) communications chip and the signal is an RF communication signal.

4. The chip package of claim 1 , wherein the plurality of electrical interfaces are solder balls.

5. The chip package of claim 1 , wherein:
the laminate substrate comprises a backside, a frontside, and lateral sides that extend between the backside and the frontside,
the chip is arranged on the backside of the laminate substrate, and
the plurality of electrical interfaces are arranged on the frontside of the laminate substrate.

6. The chip package of claim 1 , wherein:
the laminate substrate comprises a backside, a frontside, and lateral sides that extend between the backside and the frontside, and
the chip and the plurality of electrical interfaces are arranged on the frontside of the laminate substrate.

7. The chip package of claim 1 , wherein:
the laminate substrate comprises a backside, a frontside, and lateral sides that extend between the backside and the frontside,
the chip is arranged on the backside or on the frontside of the laminate substrate, and
the plurality of electrical interfaces are arranged on a lateral side of the laminate substrate.

8. The chip package of claim 1 , wherein:
the laminate substrate comprises a backside, a frontside, and lateral sides that extend between the backside and the frontside,
the chip is integrated in the laminate substrate, and
the plurality of electrical interfaces are arranged on the frontside of the laminate substrate, on the backside of the laminate substrate, or on a lateral side of the laminate substrate.

9. The chip package of claim 1 , further comprising:
a housing that encapsulates the chip and at least a portion of the laminate substrate.

10. A signal transmission system, comprising:
a chip package comprising:
a chip configured to generate or receive a signal;
a laminate substrate comprising a substrate integrated waveguide (SIW) for carrying the signal through the chip package, the SIW comprising:
a chip-to-SIW transition structure configured to couple the signal between the SIW and the chip,
a SIW-to-waveguide transition structure configured to couple the signal out of the SIW or into the SIW, wherein the SIW-to-waveguide transition structure comprises a waveguide aperture,
a first metal layer that extends in a signal propagation direction from the chip-to-SIW transition structure to the SIW-to-waveguide transition structure,
a second metal layer that extends parallel to the first metal layer, and
two rows of vias that extend in the signal propagation direction and encircle the waveguide aperture, wherein each via of the two rows of vias is connected to the first metal layer and the second metal layer; and

a plurality of electrical interfaces arranged about a periphery of the waveguide aperture, the plurality of electrical interfaces configured to receive the signal from the SIW-to-waveguide transition structure and output the signal from the chip package or to couple the signal to the SIW-to-waveguide transition structure and into the substrate integrated waveguide; and

a first metallic waveguide electrically coupled to the plurality of electrical interfaces, wherein the first metallic waveguide is configured to receive the signal output from the chip package via the plurality of electrical interfaces and transmit the signal along a propagation path or transmit the signal to the chip package via the plurality of electrical interfaces.

11. The signal transmission system of claim 10 , wherein the first metallic waveguide includes a first opening as an extension of the waveguide aperture.

12. The signal transmission system of claim 11 , wherein the first metallic waveguide is an antenna waveguide.

13. The signal transmission system of claim 11 , further comprising:
a circuit substrate comprising the first metallic waveguide, wherein the first opening extends through at least a portion of the circuit substrate and the first metallic waveguide lines interior sidewalls of the circuit substrate that define the first opening.

14. The signal transmission system of claim 13 , wherein the circuit substrate further comprises a second SIW electrically coupled to the first metallic waveguide for receiving the signal therefrom.

15. The signal transmission system of claim 11 , further comprising:
a second metallic waveguide electrically coupled to the first metallic waveguide for receiving the signal therefrom,
wherein the first metallic waveguide is interposed between the plurality of electrical interfaces and the second metallic waveguide, and
wherein the second metallic waveguide includes a second opening as an extension of the waveguide aperture.

16. The signal transmission system of claim 15 , further comprising:
a circuit substrate comprising the first metallic waveguide, wherein the first opening extends through at least a portion of the circuit substrate and the first metallic waveguide lines interior sidewalls of the circuit substrate that define the first opening, and
wherein the second metallic waveguide is an antenna waveguide.

17. The signal transmission system of claim 11 , wherein:
the laminate substrate comprises a backside, a frontside, and lateral sides that extend between the backside and the frontside,
the chip is arranged on the backside of the laminate substrate, and
the plurality of electrical interfaces are arranged on the frontside of the laminate substrate.

18. The signal transmission system of claim 11 , wherein:
the laminate substrate comprises a backside, a frontside, and lateral sides that extend between the backside and the frontside, and
the chip and the plurality of electrical interfaces are arranged on the frontside of the laminate substrate.

19. The signal transmission system of claim 11 , wherein:
the laminate substrate comprises a backside, a frontside, and lateral sides that extend between the backside and the frontside,
the chip is arranged on the backside or on the frontside

Assignees

• Infineon Technologies Ag

Inventors

• Erdoel Tuncay
• Hartner Walter
• Moeller Ulrich
• Rieder Bernhard
• Seler Ernst
• Wojnowski Maciej

Classifications

• H10W44/251

  for monolithic microwave integrated circuits [MMIC] · CPC title

• H10W44/248

  for antennas · CPC title

• H10W44/216

  Waveguides, e.g. strip lines · CPC title

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title

• H10W74/129

  forming a chip-scale package [CSP] · CPC title