Low defect high capacitance thin solid electrolyte capacitor and method of fabrication thereof

US11823836B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11823836-B2
Application numberUS-202217696345-A
CountryUS
Kind codeB2
Filing dateMar 16, 2022
Priority dateSep 17, 2019
Publication dateNov 21, 2023
Grant dateNov 21, 2023

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A method of fabricating a capacitor that includes: forming a three-dimensional structure over a substrate, the three-dimensional structure having a region with elongated pores extending towards the substrate from a top surface of the three-dimensional structure remote from the substrate or elongated columns extending away from the substrate towards the top surface of the three-dimensional structure remote from the substrate; forming a first electrode layer over a surface of the region of the three-dimensional structure, the first electrode conformal to the surface of the region; forming an intermediate layer over the first electrode layer; and forming a second electrode layer over the intermediate layer, the second electrode layer conformal to the intermediate layer, wherein forming the intermediate layer includes: forming a solid-state electrolyte layer partially conformal to the first electrode layer; and forming a dielectric layer conformal to the first electrode layer.

First claim

Opening claim text (preview).

The invention claimed is: 1. A method of fabricating a capacitor, comprising: forming a three-dimensional structure over a substrate, the three-dimensional structure comprising a region having elongated pores extending towards the substrate from a top surface of the three-dimensional structure remote from the substrate or elongated columns extending away from the substrate towards the top surface of the three-dimensional structure remote from the substrate; forming a first electrode layer over a surface of said region of the three-dimensional structure, the first electrode layer conformal to said surface of said region; forming an intermediate layer over the first electrode layer; and forming a second electrode layer over the intermediate layer, the second electrode layer conformal to the intermediate layer, wherein the forming of the intermediate layer comprises: forming a solid-state electrolyte layer partially conformal to the first electrode layer; and forming a dielectric layer conformal to the first electrode layer. 2. The method of claim 1 , wherein the solid-state electrolyte layer has a conformality to the first electrode layer greater than 50% and lower than 80% and the dielectric layer has a conformality to the first electrode layer greater than or equal to 80%. 3. The method of claim 1 , further comprising: not verifying the conformality of the solid-state electrolyte layer during fabrication of the capacitor. 4. The method of claim 1 , further comprising: forming the solid-state electrolyte layer over the first electrode layer; and forming the dielectric layer over the solid-state electrolyte layer. 5. The method of claim 4 , wherein the first electrode layer includes an oxide layer suitable for ions diffusion/insertion. 6. The method of claim 5 , wherein the first electrode layer includes a conductive layer, the oxide layer suitable for adsorption occurring at an interface between the oxide layer and the conductive layer. 7. The method of claim 4 , wherein forming the intermediate layer comprises forming another solid-state electrolyte layer over the dielectric layer. 8. The method of claim 7 , wherein the first electrode layer and the second electrode layer each includes a conductive layer and an oxide layer suitable for ions diffusion/insertion and suitable for adsorption occurring at an interface between the oxide layer and the conductive layer. 9. The method of claim 1 , further comprising: forming the dielectric layer over the first electrode layer; and forming the solid-state electrolyte layer over the dielectric layer. 10. The method of claim 9 , wherein the second electrode layer includes an oxide layer suitable for ions diffusion/insertion. 11. The method of claim 10 , wherein the second electrode layer includes a conductive layer, the oxide layer suitable for adsorption occurring at an interface between the oxide layer and the conductive layer. 12. The method of claim 1 , wherein the dielectric layer has a thickness of 5 nanometers or less. 13. A capacitor, comprising: a substrate; a three-dimensional structure disposed over the substrate, the three-dimensional structure comprising a region having elongated pores extending towards the substrate from a top surface of the three-dimensional structure remote from the substrate or elongated columns extending away from the substrate towards the top surface of the three-dimensional structure remote from the substrate; a first electrode layer disposed over a surface of said region of the three-dimensional structure, conformal to said surface of said region; an intermediate layer disposed over the first electrode layer, conformal to the first electrode layer; and a second electrode layer disposed over the intermediate layer, conformal to the intermediate layer, wherein the intermediate layer comprises: a solid-state electrolyte layer partially conformal to the first electrode layer; and a dielectric layer conformal to the first electrode layer.

Assignees

Inventors

Classifications

  • H01G11/24Primary

    characterised by structural features of the materials making up or comprised in the electrodes, e.g. form, surface area or porosity; characterised by the structural features of powders or particles used therefor · CPC title

  • H01G11/46Primary

    Metal oxides · CPC title

  • specially adapted for lithium-ion capacitors, e.g. for lithium-doping or for intercalation · CPC title

  • Solid electrolytes, e.g. gels; Additives therein · CPC title

  • specially adapted for electrodes (carbonisation or activation of carbon for the manufacture of electrodes H01G11/34) · CPC title

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What does patent US11823836B2 cover?
A method of fabricating a capacitor that includes: forming a three-dimensional structure over a substrate, the three-dimensional structure having a region with elongated pores extending towards the substrate from a top surface of the three-dimensional structure remote from the substrate or elongated columns extending away from the substrate towards the top surface of the three-dimensional struc…
Who is the assignee on this patent?
Murata Manufacturing Co, Commissariat Energie Atomique
What technology area does this patent fall under?
Primary CPC classification H01G11/24. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Nov 21 2023 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 9 related publications on this page (citations in our corpus or others sharing the same primary CPC).