Electrically programmable application-specific integrated circuit initialization engine

Patent metadata

Field	Value
Publication number	US-11822930-B2
Application number	US-201916527580-A
Country	US
Kind code	B2
Filing date	Jul 31, 2019
Priority date	Jul 31, 2019
Publication date	Nov 21, 2023
Grant date	Nov 21, 2023

Abstract

A method of initializing an application-specific integrated circuit (ASIC), the method including reading, by a boot microcode engine integrated with the ASIC, microcode from an electrically programmable non-volatile memory (EP-NVM) integrated on a same die as the ASIC. The method further includes writing the microcode onto internal memories of a micro-controller of the ASIC and initializing the micro-controller by the boot microcode engine. The method also includes loading, by the micro-controller, a full boot image from an additional storage device distinct from the EP-NVM onto the internal memories of the micro-controller and initializing the ASIC by the micro-controller based on the full boot image.

First claim

What is claimed is:

1. An application-specific integrated circuit (ASIC) comprising:
a die on which the ASIC is fabricated;
an electrically programmable non-volatile memory (EP-NVM) integrated on the die, the EP-NVM being distinct from the ASIC and including an initialization program and a boot image; and
an ASIC initialization engine including a boot microcode engine and a micro-controller, the boot microcode engine configured to initialize the micro-controller, and the micro-controller configured to:
read the initialization program from the EP-NVM integrated on the die,
write the initialization program to a micro-controller memory, and
disable external write and read access to the micro-controller memory until authentication of the boot image from the EP-NVM is completed.

2. The ASIC of claim 1 , further comprising an interface controller included in the ASIC initialization engine to drive different interfaces to transmit data and initialize a plurality of functional blocks.

3. The ASIC of claim 1 , wherein a bootstrap image is included in a plurality of executable instructions in the EP-NVM, and wherein the bootstrap image is different than the boot image.

4. The ASIC of claim 3 , wherein the micro-controller includes an instruction memory (IMEM) and a data memory (DMEM) to receive the bootstrap image to be executed by the micro-controller.

5. The ASIC of claim 4 , wherein the bootstrap image includes information that allows the micro-controller to retrieve a second boot image from a storage device other than the EP-NVM.

6. The ASIC of claim 1 , wherein a set of boot microcode for the boot microcode engine allows transfer of contents of the EP-NVM to internal memories of the micro-controller.

7. The ASIC of claim 1 , wherein contents of the EP-NVM provide information for an initialization of the ASIC initialization engine first, and other ASIC functional blocks subsequently.

8. The ASIC of claim 1 , wherein contents of the EP-NVM includes microcode and a bootstrap image.

9. The ASIC of claim 2 , wherein the interface controller allows access to a plurality of functional blocks of the ASIC.

10. A method of initializing an application-specific integrated circuit (ASIC), the method comprising:
obtaining a die on which the ASIC is fabricated;
electrically writing microcode into an electrically programmable non-volatile memory (EP-NVM) integrated on the die, wherein the EP-NVM comprises an initialization program and a boot image;
reading, by a boot microcode engine deployed within an ASIC initialization engine integrated with the ASIC, the microcode from the EP-NVM, wherein the microcode comprises the initialization program from the EP-NVM integrated on the die;
writing the microcode onto, a micro-controller memory of a micro-controller integrated with the ASIC;
disabling external write and read access to the micro-controller memory until authentication of the boot image from the EP-NVM is completed;
initializing the micro-controller by the boot microcode engine; and
initializing the ASIC by the micro-controller based on the microcode.

11. The method of claim 10 , further comprising enabling a clock and a power supply by the boot microcode engine.

12. The method of claim 10 , further comprising sending a signal from the ASIC via a general programmable input/output (GPIO) interface, the signal indicating success or failure of initialization of the ASIC.

13. The method of claim 10 , wherein the micro-controller memory of the micro-controller include an instruction memory and a data memory to hold the microcode for execution by the micro-controller.

14. The method of claim 10 , wherein the ASIC initialization engine to perform initialization of the ASIC using the initialization program from the EP-NVM integrated on the die.

15. The method of claim 14 , wherein the ASIC initialization engine further includes an interface controller to allow data transfer to initialize functional blocks of the ASIC.

16. The method of claim 10 , wherein the microcode includes a bootstrap image to enable the micro-controller to start executing software upon power-up and wherein the bootstrap image is different than the boot image.

17. A method of initializing an application-specific integrated circuit (ASIC), the method comprising:
obtaining a die on which the ASIC is fabricated;
electrically writing microcode into an electrically programmable non-volatile memory (EP-NVM) integrated on the die, wherein the EP-NVM comprises an initialization program and a boot image;
reading, by a boot microcode engine integrated with the ASIC, the microcode from the EP-NVM, wherein the microcode comprises an initialization program from the EP-NVM integrated on the die;
writing the microcode onto a micro-controller memory of a micro-controller of the ASIC;
disabling external write and read access to the micro-controller memory until authentication of the boot image from the EP-NVM is completed;
initializing the micro-controller by the boot microcode engine;
loading, by the micro-controller, a full boot image from a storage device distinct from the EP-NVM onto the micro-controller memory of the micro-controller; and
initializing the ASIC by the micro-controller based on the full boot image.

18. The method of claim 17 , wherein the storage device comprises a boot non-volatile memory.

19. The method of claim 17 , wherein the micro-controller enables a clock and a power source supporting an additional storage device prior to loading the full boot image.

20. The method of claim 17 , wherein the micro-controller uses an interface controller included in an ASIC initialization engine to access an additional storage device to load the full boot image.

Assignees

• Hewlett Packard Entpr Dev Lp

Inventors

• Maroni Peter David
• Tillema John E
• Hallinan Erin
• Howe Michael Joseph

Classifications

• G06F9/4403 Primary

  Processor initialisation · CPC title

• G06F9/24

  Loading of the microprogram · CPC title

• H03K19/1776

  for memories · CPC title

• H03K19/17772 Primary

  for powering on or off · CPC title