Print chip configured for single-pass monochrome printing at high speeds

Patent metadata

Field	Value
Publication number	US-11820139-B2
Application number	US-202117467896-A
Country	US
Kind code	B2
Filing date	Sep 7, 2021
Priority date	Sep 9, 2020
Publication date	Nov 21, 2023
Grant date	Nov 21, 2023

Abstract

A print chip includes: an elongate silicon substrate defining nominal leading and trailing longitudinal sides of the print chip; circuitry layers positioned on the silicon substrate; and a MEMS layer positioned on the circuitry layers. The MEMS layer includes a plurality of parallel nozzle rows, each nozzle row having a plurality of inkjet nozzle devices arranged in a main row portion and a dropped row portion offset from the main row portion. The circuitry layers include data latches configured to provide dot data for the inkjet nozzle devices. A first row of data latches is positioned adjacent a leading row of the main row portion, and a second row of data latches is positioned adjacent a trailing row of the dropped row portion.

First claim

The invention claimed is:

1. A print chip comprising:
an elongate silicon substrate defining nominal leading and trailing longitudinal sides of the print chip;
one or more circuitry layers positioned on the silicon substrate; and
a MEMS layer positioned on the circuitry layers, said MEMS layer comprising a plurality of parallel nozzle rows, each nozzle row comprising a plurality of inkjet nozzle devices arranged in a main row portion and a dropped row portion offset from the main row portion, wherein

the circuitry layers comprise;
a command unit for receiving rows of dot data for the print chip and dividing each row of dot data into first dot data and second data;
a first row of data latches positioned adjacent a leading row of the main row portion;
a second row of data latches positioned adjacent a trailing row of the dropped row portion; and
a buffer

wherein the command unit is configured to route the first dot data directly to the first row of data latches and route the second dot data to the second row of data latches via the buffer.

2. The print chip of claim 1 , wherein:
a first set of conductive traces extend from the first row of data latches towards the main row portion; and
a second set of conductive traces extend from the second row of data latches towards the dropped row portion in an opposite direction to the first set of conductive traces.

3. The print chip of claim 2 , wherein the dropped row portions together are arranged in a trapezoidal shape.

4. The print chip of claim 3 , wherein the trapezoidal shape has a leading nozzle row and a parallel trailing nozzle row, the trailing nozzle row being relatively longer than the leading nozzle row.

5. The print chip of claim 2 , wherein the first and second sets of conductive traces are parallel to each other.

6. The print chip of claim 1 , wherein, in use, the leading side of the print chip is upstream relative to a media feed direction.

7. The print chip of claim 1 , wherein, in use, the trailing side of the print chip is downstream relative to a media feed direction.

8. The print chip of claim 1 , wherein the command unit is positioned adjacent a trailing nozzle of the main row portion.

9. The print chip of claim 1 , wherein the buffer is configured to buffer the second dot data for a predetermined delay period before the dot data is sent to the second row of data latches.

10. The print chip of claim 9 , wherein the command unit comprises a configurable register for storing a value of the predetermined delay period.

11. The print chip of claim 9 , wherein the buffer has a data capacity corresponding to a number of nozzles in the dropped nozzle portion.

12. The print chip of claim 9 , further comprising a row of electrical pads positioned along one side of the print chip, and wherein the command unit is configured to receive the rows of dot data via the electrical pads.

13. The print chip of claim 11 , wherein the electrical pads are positioned along the trailing side of the substrate.

14. The print chip of claim 1 , wherein each nozzle row in the dropped row portion is configured to fire its inkjet nozzles independently of a corresponding nozzle row in the main row portion.

Assignees

• Memjet Technology Ltd

Inventors

• Hogan Julie Catherine
• Palliser Ronan
• Sheahan John
• Brown Brian
• Forbes Caitriona
• Lehane Pat

Classifications

• B41J2/04573 Primary

  Timing; Delays · CPC title

• B41J2/04505

  aiming at correcting alignment · CPC title

• B41J2/04541

  Specific driving circuit · CPC title

• B41J2/04586

  controlling heads of a type not covered by groups B41J2/04575 - B41J2/04585, or of an undefined type · CPC title

• B41J2/2135 Primary

  Alignment of dots · CPC title