Heat image forming device and method

Patent metadata

Field	Value
Publication number	US-11820121-B2
Application number	US-202117462043-A
Country	US
Kind code	B2
Filing date	Aug 31, 2021
Priority date	Jan 19, 2021
Publication date	Nov 21, 2023
Grant date	Nov 21, 2023

Abstract

A heating circuit having an array of switching heating elements (e.g., field effect transistors, thin film transistors) provides a transient heat pattern over a surface (e.g., substrate, imaging member surface, transfer roll surface) moving relative to the heating circuit, to produce a pixelated heat image and heat a target pattern on the surface. Heat is generated by current flow in the heating elements, and the power developed by the heating circuit is the product of source-drain voltage and current in the channel. Digital addressing may accomplished by matrix addressing the array. Current may be supplied along data address lines by an external voltage controlled by digital electronics understood by a skilled artisan to provide the desired heat at a respective heating element pixels addressed by a specific gate line. The circuit may include a current return line that may be low resistance, for example, by using a 2-dimensional mesh.

First claim

What is claimed is:

1. A heat image forming device for selectively heating an adjacent surface, comprising
an array of switching heating elements, with each heating element being a field effect transistor, the transistors each having a semiconductor layer, a gate electrode, a source electrode, a drain electrode and a dielectric layer deposited as thin-films onto a substrate, the gate electrode separated from the drain electrode and source electrode by the dielectric layer, the semiconductor layer having a current channel defined by a spatial gap between the source electrode and gate electrode, and an overlapping distance of the drain and source electrodes in the semiconductor layer;
a plurality of conductive lines including gate address lines, current supply data lines, and current return lines, with each one of the gate electrodes electronically coupled to one of the gate lines, each one of the source electrodes electronically coupled to one of the data lines, and each one of the drain electrodes electronically coupled to one of the current return lines, each heating element having a current supplied via a connecting current supply data line in the current channel that is controlled by a voltage applied to the gate electrode via a connecting gate address line;
wherein the current channel is closer to the surface being heated than the current return lines.

2. The device of claim 1 , wherein the current channel is closer to the surface than the conductive lines.

3. The device of claim 1 , wherein the current return lines are offset from the gate electrode by a second dielectric layer and opposite the drain electrode.

4. The device of claim 3 , wherein the current return lines form a current return mesh layer offset from the gate electrode by the second dielectric layer and opposite the source and drain electrodes, with different ones of the current return lines running parallel to both the gate address lines and the current supply lines.

5. The device of claim 1 , wherein the field effect transistor has a bottom gate configuration having, in order of deposition, the gate electrode, the dielectric layer, both the source electrode and the drain electrode, and the semiconductor layer.

6. The device of claim 5 , wherein one of the current return lines is deposited before the gate electrode and is in conductive contact with the drain electrode deposited above the one of the current return lines.

7. The device of claim 1 , wherein the field effect transistor has a top gate configuration having, in order of deposition, the semiconductor layer, both the source electrode and the drain electrode, the dielectric layer, the gate electrode and one of the current return lines.

8. The device of claim 7 , wherein the semiconductor layer is deposited over a release layer over a carrier, released from the carrier after the field effect transistor fabrication, and then inverted onto a support layer to place the current channel adjacent the surface being heated.

9. The device of claim 1 , further comprising a passivation layer over the semiconductor layer and adjacent the surface being heated to protect the current channel.

10. The device of claim 9 , further comprising a surface layer over the passivation layer, the surface layer having a material configured for contact with the surface being heated.

11. The device of claim 10 , wherein the surface layer material is thermally conductive.

12. The device of claim 1 , wherein the semiconductor layer includes one of an oxide semiconductor, an organic semiconductor, a polysilicon, an amorphous silicon, and carbon nanotubes.

13. The device of claim 1 , further comprising gate line drivers coupled to the gate address lines and data line drivers coupled to the current supply data lines on both ends thereof.

14. The device of claim 1 , further comprising gate line drivers coupled to the gate address lines and data line drivers coupled to the current supply data lines, wherein there is a voltage drop along the current supply data lines so that field effect transistors distal from the data line drivers have a greater voltage drop than heating elements proximal to the data line drivers, and the current channels of the field effect transistors distal from the data line drivers have a width-to-length ratio different than the field effect transistors proximal to the data line drivers.

15. A method of selectively heating an adjacent surface with the heat image forming device of claim 1 , wherein the adjacent surface includes a plurality of regions, with some of the regions including a patterned image on the surface or areas of the surface where the patterned image will be rendered, the method comprising:
a) moving the patterned image of the adjacent surface and the array of switching heating elements relative to each other,
b) during the moving, selectively switching the heating elements proximal to the patterned image to a first state based on the patterned image, and
c) heating only the regions including the patterned image or areas of the surface where the patterned image will be rendered.

16. The method of claim 15 , further comprising selectively switching the heating elements via active matrix addressing.

17. A system for selectively heating an adjacent surface with the heat image forming device of claim 1 , wherein the adjacent surface includes a plurality of regions, with some of the regions including a patterned image, the system comprising:
a processor and a memory, the memory storing instructions to cause the processor to perform:
a) moving the patterned image of the adjacent surface and the array of switching heating elements relative to each other,
b) during the moving, selectively switching the heating elements proximal to the patterned image to a first state based on the patterned image, and
c) heating only the regions including the patterned image or areas of the surface where the patterned image will be rendered.

18. The system of claim 17 , further comprising gate line drivers coupled to the gate address lines and data line drivers coupled to the current supply data lines, wherein there is a voltage drop along the current supply data lines so that heating elements distal from the data line drivers have a greater voltage drop than heating elements proximal to the data line drivers, and the memory storing further instructions to cause the processor to control the data line drivers to increase an applied voltage to heating elements at locations distal from the data line drivers.

19. A heat image forming system for selectively heating an adjacent surface, comprising
an array of switching heating elements, with each heating element having a semiconductor layer, a gate electrode, a source electrode, a drain electrode and a dielectric layer between the gate electrode and both the source and drain electrodes, the semiconductor layer having a current channel;
a plurality of conductive lines including gate address lines, current supply data lines, and current return lines, with each one of the gate electrodes electronically coupled to one of the gate lines, each one of the source electrodes electronically coupled to one of the data lines, and each one of the drain electrodes electronically coupled to one of the current return lines, each heating element having a current supplied via a connecting current supply data line in the current channel that is controlled by a voltage applied to the gate electrode via a connecting gate address line;
wherein the current return lines are offset from the gate electrode by a sec

Assignees

• Palo Alto Res Ct Inc
• Xerox Corp

Inventors

• Street Robert A
• Lu Jengping

Classifications

• B41F13/08 Primary

  Cylinders · CPC title

• B41C1/1041

  by modification of the lithographic properties without removal or addition of material, e.g. by the mere generation of a lithographic pattern · CPC title

• B41F7/02

  for offset printing · CPC title

• B41F7/08

  using one transfer cylinder co-operating with several forme cylinders for printing on sheets or webs, e.g. sampling of colours on one transfer cylinder · CPC title

• B41F7/26

  using transfer rollers · CPC title