Hamming weight calculation method based on operation apparatus

Patent metadata

Field	Value
Publication number	US-11817880-B2
Application number	US-202217895466-A
Country	US
Kind code	B2
Filing date	Aug 25, 2022
Priority date	Feb 27, 2020
Publication date	Nov 14, 2023
Grant date	Nov 14, 2023

Abstract

The present application discloses a Hamming weight calculation method performed by an operation apparatus. The operation apparatus includes a controller and a first calculator, wherein the controller sets an initial resistance state of the first memory to a low resistance state; determines a first gate voltage of the first transistor based on first bit data in a first binary sequence, and control an on-off state of the first transistor based on the first gate voltage; controls a target resistance state of the first memory based on the on-off state of the first transistor; and determines a Hamming weight of the first bit data based on a first output current on the source of the first transistor.

First claim

What is claimed is:

1. A Hamming weight calculation method performed by an operation apparatus, wherein the operation apparatus comprises a controller and a first calculator, the controller is in signal connection with the first calculator, the first calculator comprises a first memory and a first transistor, a drain of the first transistor is connected to a negative electrode of the first memory, and a source of the first transistor is grounded; and
the method is performed by the controller, and the method comprises:
setting an initial resistance state of the first memory to a low resistance state;
determining a first gate voltage of the first transistor based on first bit data in a first binary sequence taken as input, and controlling an on-off state of the first transistor based on the first gate voltage, wherein when the first bit data is 0, the first transistor is in an on state; and when the first bit data is 1, the first transistor is in an off state;
controlling a target resistance state of the first memory based on the on-off state of the first transistor, wherein when the first transistor is in the on state, the target resistance state of the first memory is a high resistance state; and when the first transistor is in the off state, the target resistance state of the first memory is the low resistance state; and
determining a Hamming weight of the first bit data based on a first output current on the source of the first transistor.

2. The method according to claim 1 , wherein the operation apparatus further comprises a second calculator, the controller is in signal connection with the second calculator, the second calculator comprises a second memory and a second transistor, a drain of the second transistor is connected to a negative electrode of the second memory, a source of the second transistor is connected to the source of the first transistor, and a positive electrode of the second memory is connected to a positive electrode of the first memory; and the method further comprises:
setting an initial resistance state of the second memory to a low resistance state;
determining a second gate voltage of the second transistor based on second bit data in the first binary sequence, and controlling an on-off state of the second transistor based on the second gate voltage, wherein when the second bit data is 0, the second transistor is in an on state; and when the second bit data is 1, the second transistor is in an off state;
controlling a target resistance state of the second memory based on the on-off state of the second transistor, wherein when the second transistor is in the on state, the target resistance state of the second memory is a high resistance state; and when the second transistor is in the off state, the target resistance state of the second memory is a low resistance state; and
determining a Hamming weight of the second bit data based on a second output current on the source of the second transistor.

3. The method according to claim 1 , wherein the determining a Hamming weight of the first bit data based on a first output current on the source of the first transistor comprises:
controlling the first transistor to be turned on;
obtaining the first output current by adjusting a voltage loaded on the first memory; and
determining the Hamming weight of the first bit data based on the first output current and a preset current.

4. The method according to claim 1 , wherein the controlling a target resistance state of the first memory based on the on-off state of the first transistor comprises:
controlling the target resistance state of the first memory by adjusting the voltage loaded on the first memory.

5. The method according to claim 1 , wherein the setting an initial resistance state of the first memory to a low resistance state comprises:
turning on the first transistor; and
setting the initial resistance state of the first memory to the low resistance state by adjusting the voltage loaded on the first memory.

6. The method according to claim 1 , wherein the operation apparatus further comprises a third calculator, the controller is in signal connection with the third calculator, the third calculator comprises a third memory and a third transistor, a drain of the third transistor is connected to a negative electrode of the third memory, a source of the third transistor is grounded, and a gate of the third transistor is connected to a gate of the first transistor; and the method further comprises:
setting an initial resistance state of the third memory to a low resistance state;
determining a third gate voltage of the third transistor based on third bit data in a second binary sequence taken as input, and controlling an on-off state of the third transistor based on the third gate voltage, wherein when the third bit data is 0, the third transistor is in an on state; and when the third bit data is 1, the third transistor is in an off state;
controlling a target resistance state of the third memory based on the on-off state of the third transistor, wherein when the third transistor is in the on state, the target resistance state of the third memory is a high resistance state; and when the third transistor is in the off state, the target resistance state of the third memory is a low resistance state; and
determining a Hamming weight of the third bit data based on a third output current on the source of the third transistor.

7. The method according to claim 1 , wherein a type of the first memory comprises non-volatile memory, and a type of the first transistor comprises metal-oxide semiconductor field-effect transistor.

8. A controller, wherein the controller is in signal connection with a first calculator, the first calculator comprises a first memory and a first transistor, a drain of the first transistor is connected to a negative electrode of the first memory, and a source of the first transistor is grounded; and
the controller is configured to set an initial resistance state of the first memory to a low resistance state;
determine a first gate voltage of the first transistor based on first bit data in a first binary sequence taken as input, and control an on-off state of the first transistor based on the first gate voltage, wherein when the first bit data is 0, the first transistor is in an on state, and when the first bit data is 1, the first transistor is in an off state; and
control a target resistance state of the first memory based on the on-off state of the first transistor, wherein when the first transistor is in the on state, the target resistance state of the first memory is a high resistance state, and when the first transistor is in the off state, the target resistance state of the first memory is the low resistance state; and
the controller further comprises a Hamming weight obtainer circuit that is configured to determine a Hamming weight of the first bit data based on a first output current on the source of the first transistor.

9. The controller according to claim 8 , wherein the controller is further in signal connection with a second calculator, the second calculator comprises a second memory and a second transistor, a drain of the second transistor is connected to a negative electrode of the second memory, a source of the second transistor is connected to the source of the first transistor, and a positive electrode of the second memory is connected to a positive electrode of the first memory;
the controller is further configured to:
set an initial resistance state of the second memory to a low resistance state;
determine a second gate voltage of the second transistor based on second bit data in the first binary sequence, and control an on-off state of the second transistor base

Assignees

• Huawei Tech Co Ltd

Inventors

• Li Yi
• Li Jiancong
• Miao Xiangshui
• Yan Peng
• Pu Guiyou
• Shi Xiaozhong
• Huang Keji

Classifications

• H03M13/19 Primary

  Single error correction without using particular properties of the cyclic codes, e.g. Hamming codes, extended or generalised Hamming codes · CPC title

• H03M13/611

  Specific encoding aspects, e.g. encoding by means of decoding · CPC title

• H04L9/0863 Primary

  involving passwords or one-time passwords (network architectures or network communication protocols for using one-time keys in a packet data network H04L63/067) · CPC title

• G06F7/607 Primary

  number-of-ones counters, i.e. devices for counting the number of input lines set to ONE among a plurality of input lines, also called bit counters or parallel counters (for applications thereof, see the relevant places, e.g. G06F7/49, G06F7/5013, G06F7/509, H03M1/00, H03M7/20) · CPC title

• G06F7/38

  Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation · CPC title