Electronic apparatus

Patent metadata

Field	Value
Publication number	US-11817388-B2
Application number	US-202217851046-A
Country	US
Kind code	B2
Filing date	Jun 28, 2022
Priority date	Jul 29, 2019
Publication date	Nov 14, 2023
Grant date	Nov 14, 2023

Abstract

The disclosure provides an electronic apparatus. The electronic apparatus includes a substrate, a first metal layer, an insulating layer, a first conductor, an electronic assembly and a transistor circuit die. The first metal layer is disposed on the substrate. The insulating layer is disposed on the substrate. The first conductor is formed in a first via of the insulating layer. The electronic assembly is disposed on the substrate and electrically connected to the first metal layer through the first conductor. The transistor circuit die is electrically connected to the first metal layer.

First claim

What is claimed is:

1. An electronic apparatus, comprising:
a substrate;
a first metal layer, disposed on the substrate;
an insulating layer, disposed on the substrate;
a first conductor, formed in a first via of the insulating layer;
an electronic assembly, disposed on the substrate and electrically connected to the first metal layer through the first conductor; and
a transistor circuit die, electrically connected to the first metal layer.

2. The electronic apparatus of claim 1 , wherein the transistor circuit die comprises:
a glass substrate; and
at least one transistor, formed on the glass substrate.

3. The electronic apparatus of claim 1 , wherein the electronic assembly is a PN junction assembly.

4. The electronic apparatus of claim 3 , wherein the electronic assembly comprises a variable capacitor.

5. The electronic apparatus of claim 1 , wherein the first metal layer comprises at least one bonding pad.

6. The electronic apparatus of claim 1 , further comprising:
a second metal layer, disposed on the substrate; and
a second conductor, formed in a second via of the insulating layer, and electrically connected to the electronic assembly and the second metal layer.

7. The electronic apparatus of claim 6 , further comprising:
another insulating layer, disposed between the first metal layer and the second metal layer.

8. The electronic apparatus of claim 1 , further comprising:
a control circuit,
wherein the transistor circuit die receives a control signal from the control circuit and drives the electronic assembly.

9. The electronic apparatus of claim 1 , wherein the electronic assembly comprises a light emitting diode.

Assignees

• Innolux Corp

Inventors

• Hung Tang Chin
• Ting Chin-Lung
• Wei Chung-Kuang
• Kao Ker-Yih
• Wang Tong-Jung
• Hsieh Chih-Yung
• Huang Hao Jung
• Li I-Yin
• Ho Chia-Chi
• Lin Yi Hung
• Chou Cheng-Hsu
• Tseng Chia-Ping

Classifications

• H10W70/614

  the multiple chips being integrally enclosed · CPC title

• H10W90/10

  Configurations of laterally-adjacent chips · CPC title

• H10W90/401

  characterised by multiple insulating or insulated package substrates, interposers or RDLs · CPC title

• H10W70/611 Primary

  for connecting multiple chips together · CPC title

• H10W20/496

  Capacitor integral with wiring layers · CPC title