Runtime configuration of chipset to support multiple I/O subsystem versions with one BIOS image

Patent metadata

Field	Value
Publication number	US-11816491-B2
Application number	US-202117375911-A
Country	US
Kind code	B2
Filing date	Jul 14, 2021
Priority date	Jul 14, 2021
Publication date	Nov 14, 2023
Grant date	Nov 14, 2023

Abstract

A method for configuring a peripheral bus of an information handling system performs, as part of a boot sequence, an initial configuration of a chipset setting pertaining to the bus based on a descriptor stored in a nonvolatile storage resource. After an operating system is loaded, a controller detects a peripheral device connecting to the bus and responds by performing a runtime configuration of the chipset setting based on capability information obtained from the peripheral device. The peripheral bus may comprise a USB pipe and a USB-C type connector, wherein the peripheral device is detected by a USB power delivery (PD) controller based on configuration channel (CC) pins of the USB-C connector. The PD controller may signal the chipset and send the device’s capability information to the chipset. The PD controller may assert a PMCALERT# signal of the chipset’s and send the capability information via a system management link (SMLink1).

First claim

What is claimed is:

1 . A method for configuring a peripheral bus of an information handling system, wherein the method comprises:
performing an initial configuration, in accordance with a descriptor stored in a nonvolatile storage resource of the information handling system, of a chipset setting associated with the peripheral bus; after performing the initial configuration, detecting a peripheral device connecting to the peripheral bus; receiving capability information, indicative of a capability of the peripheral bus; and responsive to receiving the capability information, performing a runtime configuration of the chipset setting in accordance with the capability information wherein the initial configuration is performed by system BIOS during a boot sequence and wherein detecting the peripheral device and reconfiguring the chipset setting occurs after an operating system is loaded.

2 . The method of claim 1 , wherein the peripheral bus comprises a universal serial bus (USB) pipe and wherein a USB-C connector connects the peripheral device to the USB pipe.

3 . The method of claim 2 , wherein detecting the peripheral device connecting to the USB pipe comprises detecting, by a power delivery (PD) controller, an assertion of a configuration channel (CC) pin.

4 . The method of claim 3 , wherein the PD controller is configured to respond to said detecting by signaling the chipset and sending capability information to the chipset.

5 . The method of claim 4 , wherein the PD controller is configured to send capability information to the chipset via a system management link to which the PD controller and the chipset are connected.

6 . The method of claim 3 , wherein the PD controller is configured to respond to said detecting by sending capability information to a PD re-timer.

7 . The method of claim 3 , wherein the initial configuration comprises a USB 3.2 Gen2×1 configuration and the runtime configuration comprises a USB 3.2 Gen2×2 configuration.

8 . The method of claim 3 , wherein the initial configuration comprises a USB 3.2 Gen2×2 configuration and the runtime configuration comprises a USB 3.2 Gen2×1 configuration.

9 . An information handling system, comprising:
a central processing unit (CPU); a chipset configured to couple a peripheral bus to the CPU; and system memory communicatively coupled to the CPU, including processor executable instructions that, when executed by the processor, cause the system to perform peripheral bus configuration operations comprising:
performing an initial configuration, in accordance with a descriptor stored in a nonvolatile storage resource of the information handling system, of a chipset setting associated with the peripheral bus;
after performing the initial configuration, detecting a peripheral device connecting to the peripheral bus;
receiving capability information, indicative of a capability of the peripheral bus; and
responsive to receiving the capability information, performing a runtime configuration of the chipset setting in accordance with the capability information
wherein the peripheral bus comprises a universal serial bus (USB) pipe and wherein a USB-C connector connects the peripheral device to the USB pipe.

10 . The information handling system of claim 9 , wherein the initial configuration is performed by system BIOS during a boot sequence and wherein detecting the peripheral device and reconfiguring the chipset setting occurs after an operating system is loaded.

11 . The information handling system of claim 9 , wherein detecting the peripheral device connecting to the USB pipe comprises detecting, by a power delivery (PD) controller, an assertion of a configuration channel (CC) pin.

12 . The information handling system of claim 11 , wherein the PD controller is configured to respond to said detecting by signaling the chipset and sending capability information to the chipset.

13 . The information handling system of claim 12 , wherein the PD controller is configured to send capability information to the chipset via a system management link to which the PD controller and the chipset are connected.

14 . The information handling system of claim 11 , wherein the PD controller is configured to respond to said detecting by sending capability information to a PD re-timer.

15 . The information handling system of claim 11 , wherein the initial configuration comprises a USB 3.2 Gen2×1 configuration and the runtime configuration comprises a USB 3.2 Gen2×2 configuration.

16 . The information handling system of claim 11 , wherein the initial configuration comprises a USB 3.2 Gen2×2 configuration and the runtime configuration comprises a USB 3.2 Gen2×1 configuration.

Assignees

• Dell Products Lp

Inventors

• Leara William D
• Juan Chien-Yi
• Wang rong-yu
• Chiu Jui-Hsing

Classifications

• G06F9/4411 Primary

  Configuring for operating with peripheral devices; Loading of device drivers · CPC title

• G06F13/4282

  on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title

• G06F2213/0042

  Universal serial bus [USB] · CPC title

• G06F13/4295 Primary

  using an embedded synchronisation · CPC title