Enterprise host memory buffer

Patent metadata

Field	Value
Publication number	US-11816337-B2
Application number	US-202117543473-A
Country	US
Kind code	B2
Filing date	Dec 6, 2021
Priority date	Dec 6, 2021
Publication date	Nov 14, 2023
Grant date	Nov 14, 2023

Abstract

A storage system includes one or more data storage devices, a PCIe switch coupled to the one or more data storage devices, and a controller unit coupled to the PCIe switch. The controller unit includes a dynamic random access memory (DRAM) host memory buffer (HMB) controller and a DRAM pool or a controller memory buffer (CMB) controller, a root complex/port, and the DRAM pool. The DRAM pool includes one or more DRAM devices. The one or more data storage devices are configured to interact with the controller unit and store data to a DRAM of the DRAM pool of the controller unit.

First claim

What is claimed is:

1. A storage system, comprising:
one or more data storage devices;
a PCIe switch coupled to the one or more data storage devices; and
a controller unit coupled to the PCIe switch, wherein:
the controller unit is a data storage device; and
the data storage device is distinct from the one or more data storage devices, the controller unit comprising:
a dynamic random access memory (DRAM) host memory buffer (HMB) controller for controlling one or more DRAM devices of the controller unit distinct from an HMB of a host device; and
a DRAM pool, wherein:
the DRAM pool comprises the one or more DRAM devices disposed in the controller unit; and
each of the one or more DRAM devices is allocated by the DRAM HMB controller to the one or more data storage devices for use by the one or more data storage devices.

2. The storage system of claim 1 , wherein the PCIe switch is directly coupled to the DRAM HMB controller.

3. The storage system of claim 1 , wherein each data storage device of the one or more data storage devices comprises:
a HMB controller;
a PCIe/NVMe front end unit;
a memory device management unit;
a memory device interface unit; and
a memory device.

4. The storage system of claim 1 , wherein the controller unit acts as a root complex for the one or more data storage devices.

5. The storage system of claim 1 , wherein the one or more data storage devices are distinct from the controller unit.

6. The storage system of claim 1 , wherein the controller unit appears as a peer PCIe device to the one or more data storage devices.

7. The storage system of claim 1 , wherein the DRAM pool is shared by the one or more data storage devices.

8. The storage system of claim 1 , wherein the one or more data storage devices is two or more data storage devices.

9. The storage system of claim 1 , wherein each data storage device of the one or more data storage devices comprises a first port and a second port, and wherein the first port is coupled to the PCIe switch.

10. A storage system, comprising:
a first data storage device;
a second data storage device;
a PCIe switch coupled to the first data storage device and the second data storage device; and
a controller unit coupled to the first data storage device and the second data storage device, wherein:
the controller unit is a data storage device; and
the data storage device is distinct from the first data storage device and the second data storage device, the controller unit comprising:
a dynamic random access memory (DRAM) host memory buffer (HMB) controller for controlling one or more DRAM devices of the controller unit distinct from an HMB of a host device; and
a DRAM pool, wherein:
the DRAM pool comprises the one or more DRAM devices disposed in the controller unit; and
each of the one or more DRAM devices is allocated by the DRAM HMB controller to the first data storage device and the second data storage device for use by the first data storage device and the second data storage device.

11. The storage system of claim 10 , wherein the first data storage device and the second data storage device each have a first port and a second port, and wherein the first port is coupled to the PCIe switch.

12. The storage system of claim 11 , wherein the second port is coupled to the controller unit.

13. The storage system of claim 12 , wherein the second port is coupled to a HMB controller.

14. The storage system of claim 13 , wherein the HMB controller is disposed in the first data storage device and the second data storage device.

15. The storage system of claim 12 , wherein the second port is coupled to the DRAM HMB controller.

16. The storage system of claim 10 , wherein the controller unit is configured to, upon detecting a power failure event of the controller unit, push data of the DRAM pool to either the first data storage device, the second data storage device, or both first data storage device and the data storage device.

17. A storage system, comprising:
a first data storage device comprising a first memory means;
a second data storage device comprising a second memory means;
a PCIe switch coupled to the first data storage device and the second data storage device; and
a controller unit coupled to the first data storage device and the second data storage device, wherein:
the controller unit is a data storage device; and
the data storage device is distinct from the first data storage device and the second data storage device, the controller unit comprising:
a controller memory buffer (CMB) controller for controlling one or more DRAM devices of the controller unit distinct from an HMB of a host device;
a root complex/port; and
a dynamic random access memory (DRAM) pool, wherein:
the DRAM pool comprises the one or more DRAM devices disposed in the controller unit; and
each of the one or more DRAM devices is allocated by the CMB controller to the first data storage device and the second data storage device for use by the first data storage device and the second data storage device.

18. The storage system of claim 17 , wherein the first data storage device, the second data storage device, and the controller unit each comprises:
a memory means interface;
a memory means management unit; and
a PCIe/NVMe front end unit.

19. The storage system of claim 17 , wherein the first data storage device and the second data storage device each comprises a first port and a second port, wherein the first port is coupled to the PCIe switch, and wherein the second port is coupled to the root complex/port.

20. The storage system of claim 17 , wherein the CMB controller is coupled to the DRAM pool.

Assignees

• Western Digital Tech Inc

Inventors

• Hahn Judah Gamliel
• Hodes Avichay Haim
• Benisty Shay
• James Michael

Classifications

• G06F3/0616 Primary

  in relation to life time, e.g. increasing Mean Time Between Failures [MTBF] · CPC title

• G06F3/0656

  Data buffering arrangements · CPC title

• G06F3/0658

  Controller construction arrangements · CPC title

• G06F3/0688

  Non-volatile semiconductor memory arrays · CPC title

• G06F13/1673

  using buffers · CPC title