Dynamic random access memory (DRAM) component for high-performance, high-capacity registered memory modules

Patent metadata

Field	Value
Publication number	US-11815940-B2
Application number	US-202217748762-A
Country	US
Kind code	B2
Filing date	May 19, 2022
Priority date	Dec 19, 2014
Publication date	Nov 14, 2023
Grant date	Nov 14, 2023

Abstract

The embodiments described herein describe technologies of dynamic random access memory (DRAM) components for high-performance, high-capacity registered memory modules, such as registered dual in-line memory modules (RDIMMs). One DRAM component may include a set of memory cells and steering logic. The steering logic may include a first data interface and a second data interface. The first and second data interfaces are selectively coupled to a controller component in a first mode and the first data interface is selectively coupled to the controller component in a second mode and the second data interface is selectively coupled to a second DRAM component in the second mode.

First claim

What is claimed is:

1. A memory package comprising:
a package substrate comprising at least two package interfaces; and
a dual-ported stack comprising a plurality of homogeneous memory devices stacked on the package substrate, wherein:
a first memory device of the plurality of homogeneous memory devices comprises:
a first external data interface that connects to a first package interface of the at least two package interfaces on the package substrate; and
a first internal data interface that connects to all other memory devices of the plurality of homogeneous memory devices in the dual-ported stack; and

a second memory device of the plurality of homogenous memory devices comprises:
a second external data interface that connects to a second package interface of the at least two package interfaces on the package substrate; and
a second internal data interface that connects to all other memory devices of the plurality of homogeneous memory devices in the dual-ported stack.

2. The memory package of claim 1 , wherein:
a third memory device of the plurality of homogeneous memory devices comprises:
a third external data interface that does not connect to the at least two package interfaces on the package substrate; and
a third internal data interface that connects to all other memory devices of the plurality of homogeneous memory devices in the dual-ported stack; and

a fourth memory device of the plurality of homogenous memory devices comprises:
a fourth external data interface that does not connect to the at least two package interfaces on the package substrate; and
a fourth internal data interface that connects to all other memory devices of the plurality of homogeneous memory devices in the dual-ported stack.

3. The memory package of claim 1 , wherein the package substrate is disposed on a first side of a memory module substrate, wherein a second side of the memory module substrate comprises a second package substrate comprising at least two additional package interfaces and a second dual-ported stack comprising a second plurality of homogeneous memory devices stacked on the second packaged substrate.

4. The memory package of claim 1 , wherein the first memory device and the second memory device each comprises steering logic to enable a bypass path through the dual-ported stack.

5. The memory package of claim 1 , wherein the first memory device is located at a first side of the dual-ported stack that is disposed on a first surface of the package substrate, and wherein the second memory device is located at a second side of the dual-ported stack that is disposed farthest from the first surface of the package substrate.

6. The memory package of claim 5 , wherein the second external data interface connects to the second package interface on the package substrate via wire bonding interconnects.

7. The memory package of claim 1 , wherein the second external data interface connects to the second package interface on the package substrate via the first memory device using through-silicon-via (TSV) connections through the plurality of homogeneous memory devices of the dual-ported stack.

8. The memory package of claim 1 , wherein the first internal data interface and the second internal data interface are not coupled to the package substrate, wherein the first external data interface and the second external data interface are coupled to the package substrate, and wherein an access to any of the plurality of homogeneous memory devices in the dual-ported stack is made through at least one of the first package interface or the second package interface, wherein the dual-ported stack is operable to transfer data from the first package interface to the second package interface through the first internal data interface and the second internal data interface, and wherein the dual-ported stack is operable to transfer data from the second package interface to the first package interface through the second internal data interface and the first internal data interface.

9. A memory module comprising:
a first package substrate comprising at least two package interfaces; and
a first dual-ported stack comprising a plurality of homogeneous memory devices stacked on the first package substrate, wherein:
a first memory device of the plurality of homogeneous memory devices comprises:
a first external data interface that connects to a first package interface of the at least two package interfaces on the first package substrate; and
a first internal data interface that connects to all other memory devices of the plurality of homogeneous memory devices in the first dual-ported stack; and

a second memory device of the plurality of homogenous memory devices comprises:
a second external data interface that connects to a second package interface of the at least two package interfaces on the first package substrate; and
a second internal data interface that connects to all other memory devices of the plurality of homogeneous memory devices in the first dual-ported stack.

10. The memory module of claim 9 , wherein:
a third memory device of the plurality of homogeneous memory devices comprises:
a third external data interface that does not connect to the at least two package interfaces on the first package substrate; and
a third internal data interface that connects to all other memory devices of the plurality of homogeneous memory devices in the first dual-ported stack; and

a fourth memory device of the plurality of homogenous memory devices comprises:
a fourth external data interface that does not connect to the at least two package interfaces on the first package substrate; and
a fourth internal data interface that connects to all other memory devices of the plurality of homogeneous memory devices in the first dual-ported stack.

11. The memory module of claim 9 , further comprising:
a memory module substrate, wherein the first package substrate is disposed on a first side of the memory module substrate;
a second package substrate comprising at least two additional package interfaces, wherein the second package substrate is disposed on a second side of the memory module substrate; and
a second dual-ported stack comprising a second plurality of homogeneous memory devices stacked on the second packaged substrate, wherein:
a third memory device of the second plurality of homogeneous memory devices comprises:
a third external data interface that connects to a third package interface of the at least two additional package interfaces on the second package substrate; and
a third internal data interface that connects to all other memory devices of the second plurality of homogeneous memory devices in the second dual-ported stack; and

a fourth memory device of the second plurality of homogenous memory devices comprises:
a fourth external data interface that connects to a fourth package interface of the at least two additional package interfaces on the second package substrate; and
a fourth internal data interface that connects to all other memory devices of the second plurality of homogeneous memory devices in the second dual-ported stack.

12. The memory module of claim 9 , wherein the first memory device and the second memory device each comprises steering logic to enable a bypass path through the first dual-ported stack.

13. The memory module of claim 9 , wherein the first memory device is located at a first side of the first dual-ported stack that is disposed on a first surface of the first package substrate, and wherein the second memory device is located at a second side of the first dual-ported stack that is disposed farthest from the first

Assignees

• Rambus Inc

Inventors

• Ware Frederick A
• Tsern Ely
• Linstadt John Eric
• Giovannini Thomas J
• Wright Kenneth L

Classifications

• G06F13/287 Primary

  Multiplexed DMA (G06F13/30 takes precedence) · CPC title

• G06F13/16

  for access to memory bus (G06F13/28 takes precedence) · CPC title

• G11C5/04

  Supports for storage elements {, e.g. memory modules}; Mounting or fixing of storage elements on such supports · CPC title

• G11C7/10

  Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers · CPC title

• G11C7/1045

  Read-write mode select circuits · CPC title