Programming a coarse grained reconfigurable array through description of data flow graphs

Patent metadata

Field	Value
Publication number	US-11815935-B2
Application number	US-202217705099-A
Country	US
Kind code	B2
Filing date	Mar 25, 2022
Priority date	Mar 25, 2022
Publication date	Nov 14, 2023
Grant date	Nov 14, 2023

Abstract

An assembly language program for a coarse grained reconfiguration array (CGRA), having dispatch interface information indicating operations to be performed via a dispatch interface of the CGRA to receive an input, memory interface information indicating operations to be performed via one or more memory interfaces of the CGRA, tile memory information indicating memory variables referring to memory locations to be implemented in tile memories of the CGRA, a flow description specifying one or more synchronous data flows, through the memory locations referenced via the memory variables in the tile memory information, to produce a result from the input using the CGRA.

First claim

What is claimed is:

1. A method, comprising:
identifying dispatch interface information representing operations to be performed via a dispatch interface of a coarse grained reconfigurable array to receive an input;
identifying memory interface information representing operations to be performed via one or more memory interfaces of the coarse grained reconfigurable array;
identifying tile memory information about a set of memory variables referring to memory locations to be implemented in tile memories of the coarse grained reconfigurable array;
identifying one or more synchronous data flows, through memory locations referenced via the memory variables in the tile memory information, to produce a result from the input; and
generating an assembly language program containing the dispatch interface information, the memory interface information, the tile memory information, and a flow description specifying the one or more data flows.

2. The method of claim 1 , wherein the coarse grained reconfigurable array includes a plurality of tiles interconnected via synchronous connections and asynchronous connections, each of the tiles having tile memories and a reconfigurable computing logic.

3. The method of claim 2 , wherein the memory interface information and the dispatch interface information identify memory operations implemented via the asynchronous connections, and types of data to be operated upon by the memory operations.

4. The method of claim 3 , wherein the dispatch interface information identifies operations of storing inputs, received via arguments of the assembly language program, into memory locations referred to via first memory variables.

5. The method of claim 4 , wherein the memory interface information identifies operations of storing data to, or retrieving data from, memory locations referred to via second memory variables.

6. The method of claim 5 , wherein the tile memory information further identifies access types of the set of memory variables when implemented in the coarse grained reconfigurable array.

7. The method of claim 5 , wherein the set of memory variables includes the first memory variables, the second memory variables, and at least one third memory variable referring to a memory location in the one or more synchronous data flows; and the one or more synchronous data flows use fourth variables not mapped for implementation in tile memories.

8. The method of claim 7 , further comprising:
mapping the one or more synchronous data flows to flows of data in the coarse grained reconfigurable array, including mapping the set of memory variables to tile memories in the coarse grained reconfigurable array.

9. The method of claim 7 , further comprising:
compiling a computer program to generate the assembly language program.

10. The method of claim 7 , further comprising:
receiving user inputs to identify the dispatch interface information, the memory interface information, the tile memory information, and the one or more synchronous data flows;
wherein the assembly language program is generated based on the user inputs.

11. A computing device, comprising:
a memory; and
a microprocessor coupled with the memory and configured via instructions to:
identify dispatch interface information representing operations to be performed via a dispatch interface of a coarse grained reconfigurable array to receive an input;
identify memory interface information representing operations to be performed via one or more memory interfaces of the coarse grained reconfigurable array;
identify tile memory information about a set of memory variables referring to memory locations to be implemented in tile memories of the coarse grained reconfigurable array;
identify one or more synchronous data flows, through memory locations referenced via the memory variables in the tile memory information, to produce a result from the input; and
generate an assembly language program containing the dispatch interface information, the memory interface information, the tile memory information, and a flow description specifying the one or more synchronous data flows.

12. The computing device of claim 11 , wherein the coarse grained reconfigurable array includes a plurality of tiles interconnected via synchronous connections and asynchronous connections, each of the tiles having tile memories and a reconfigurable computing logic.

13. The computing device of claim 12 , wherein the tile memory information identifies access types of the set of memory variables.

14. The computing device of claim 13 , wherein the dispatch interface information identifies operations of storing inputs, received via arguments of the assembly language program, into memory locations referred to via first memory variables; and the memory interface information identifies operations of storing data to, or retrieving data from, memory locations referred to via second memory variables.

15. The computing device of claim 14 , wherein the memory interface information and the dispatch interface information identify memory operations implemented via the asynchronous connections, and types of data to be operated upon by the memory operations.

16. The computing device of claim 14 , wherein the microprocessor is further configured via the instructions to:
map the one or more synchronous data flows to flows of data in the coarse grained reconfigurable array, including mapping the set of memory variables to tile memories in the coarse grained reconfigurable array, wherein the one or more synchronous data flows go through at least fourth variables not mapped to tile memories.

17. The computing device of claim 14 , the microprocessor is further configured via the instructions to:
compile a computer program to generate the assembly language program.

18. A non-transitory computer storage medium storing instructions which, when executed by a computing device, cause the computing device to perform a method, comprising:
identifying dispatch interface information representing operations to be performed via a dispatch interface of a coarse grained reconfigurable array to receive an input;
identifying memory interface information representing operations to be performed via one or more memory interfaces of the coarse grained reconfigurable array;
identifying tile memory information about a set of memory variables referring to memory locations to be implemented in tile memories of the coarse grained reconfigurable array;
identifying one or more synchronous data flows, through memory locations referenced via the memory variables in the tile memory information, to produce a result from the input; and
generating an assembly language program containing the dispatch interface information, the memory interface information, the tile memory information, and a flow description specifying the one or more synchronous data flows.

19. The non-transitory computer storage medium of claim 18 , wherein the dispatch interface information is configured to identify:
operations of storing inputs, received via arguments of the assembly language program, into memory locations referred to via first memory variables in the set of memory variables; and
data types of the inputs;
wherein the memory interface information is configured to identify:
operations of storing or retrieving data items to or from memory locations referred to via second memory variables in the set of memory variables; and
data types of the data items; and

wherein the tile memory information is configured to identify access types of the se

Assignees

• Micron Technology Inc

Inventors

• Windh Skyler Arron
• Porterfield Allan Kennedy
• Vanesko Douglas John
• Meyer Randall Paul
• Estep Patrick Alan
• Romanous Bashar

Classifications

• G06F8/453 Primary

  Data distribution · CPC title

• G06F8/433

  Dependency analysis; Data or control flow analysis · CPC title

• G06F8/451 Primary

  Code distribution (considering CPU load at run-time G06F9/505; load rebalancing G06F9/5083) · CPC title

• G06F8/457

  Communication (intertask communication G06F9/54) · CPC title

• G06F8/458

  Synchronisation, e.g. post-wait, barriers, locks (synchronisation among tasks G06F9/52) · CPC title