Display substrate having a projection of the display layer located within a projection of a light shielding layer, display device and transparent display including the same

Patent metadata

Field	Value
Publication number	US-11812640-B2
Application number	US-202117522507-A
Country	US
Kind code	B2
Filing date	Nov 9, 2021
Priority date	Sep 30, 2018
Publication date	Nov 7, 2023
Grant date	Nov 7, 2023

Abstract

An OLED substrate is provided, which comprises a light emitting region and a transparent region, wherein the OLED substrate comprises a substrate and a display layer on the substrate, and a portion of the display layer located in the transparent region has a first hollow part. A method for manufacturing an OLED substrate and a transparent display comprising an OLED substrate are further provided.

First claim

What is claimed is:

1. A display substrate comprising:
a light emitting region; and
a transparent region,
wherein the display substrate comprises a base substrate and a display layer on the base substrate,
wherein a light shielding layer is located between the base substrate and the display layer, and
wherein an orthographic projection of the display layer on the base substrate is at least partially located within an orthographic projection of the light shielding layer on the base substrate.

2. The display substrate according to claim 1 ,
wherein the display layer comprises wirings, and
wherein an orthographic projection of the wirings on the base substrate is at least partially located within the orthographic projection of the light shielding layer on the base substrate.

3. The display substrate according to claim 2 , wherein the wirings are formed of a same material in a same layer as at least one layer of the display layer.

4. The display substrate according to claim 2 ,
wherein the wirings comprise a plurality of gate lines, and
wherein an orthographic projection of the plurality of gate lines on the base substrate is located within the orthographic projection of the light shielding layer on the base substrate.

5. The display substrate according to claim 2 ,
wherein the wirings comprise a plurality of data lines, and
wherein an orthographic projection of the plurality of data lines on the base substrate is located within the orthographic projection of the light shielding layer on the base substrate.

6. The display substrate according to claim 2 ,
wherein the wirings comprise a plurality of control lines, and
wherein an orthographic projection of the plurality of control lines on the base substrate is located within the orthographic projection of the light shielding layer on the base substrate.

7. The display substrate according to claim 2 , further comprising:
a transparent etch barrier layer located between the wirings and the light shielding layer.

8. The display substrate according to claim 7 ,
wherein the light shielding layer comprises a metal layer, and
wherein the transparent etch barrier layer comprises a transparent conductive layer.

9. The display substrate according to claim 1 , wherein the light shielding layer comprises one or more of a black resin layer or a metal layer.

10. The display substrate according to claim 1 ,
wherein the display layer comprises a buffer layer, a thin film transistor, a planarization layer, a light emitting device, and a pixel defining layer in sequence on the base substrate, and
wherein the light shielding layer is between the buffer layer and the base substrate.

11. The display substrate according to claim 1 ,
wherein the display substrate comprises a plurality of pixel units arranged in a matrix,
wherein each pixel unit of the plurality of pixel units comprises at least one sub-pixel unit,
wherein each sub-pixel unit of the at least one sub-pixel unit comprises a light emitting sub-region and a transparent sub-region, and
wherein all light emitting sub-regions constitute the light emitting region, and all transparent sub-regions constitute the transparent region.

12. The display substrate according to claim 1 ,
wherein the display substrate comprises a plurality of pixel units arranged in a matrix,
wherein each pixel unit of the plurality of pixel units comprises at least one sub-pixel unit,
wherein all sub-pixel units constitute the light emitting region, and
wherein regions among the plurality of pixel units constitute the transparent region.

13. The display substrate according to claim 1 , wherein an orthographic projection of the transparent region on the base substrate is located outside of the orthographic projection of the light shielding layer on the base substrate.

14. A display device comprising the display substrate according to claim 1 and a package layer on the display substrate.

15. The display device according to claim 14 , wherein the package layer comprises one of a substrate package layer or a thin film package layer.

16. The display device according to claim 14 ,
wherein the display layer comprises wirings, and
wherein an orthographic projection of the wirings on the base substrate is located within the orthographic projection of the light shielding layer on the base substrate.

17. The display device according to claim 16 , wherein the wirings are formed of a same material in a same layer as at least one layer of the display layer.

18. The display device according to claim 16 ,
wherein the wirings comprise a plurality of gate lines, and
wherein an orthographic projection of the plurality of gate lines on the base substrate is located within the orthographic projection of the light shielding layer on the base substrate.

19. The display device according to claim 16 ,
wherein the wirings comprise a plurality of data lines, and
wherein an orthographic projection of the plurality of data lines on the base substrate is located within the orthographic projection of the light shielding layer on the base substrate.

20. A transparent display comprising the display substrate according to claim 1 and a package layer on the display substrate.

Assignees

• Boe Technology Group Co Ltd

Inventors

• Wang Hejin
• Hsieh Mingche
• Wang Pinfan

Classifications

• H10K59/122 Primary

  Pixel-defining structures or layers, e.g. banks · CPC title

• H10K59/126

  Shielding, e.g. light-blocking means over the TFTs · CPC title

• H10K59/131

  Interconnections, e.g. wiring lines or terminals · CPC title

• H10K59/12 Primary

  Active-matrix OLED [AMOLED] displays · CPC title

• H10K59/121 Primary

  characterised by the geometry or disposition of pixel elements · CPC title