Three-dimensional memory devices containing structures for controlling gate-induced drain leakage current and method of making the same
US-2021265380-A1 · Aug 26, 2021 · US
Semiconductor memory device including select transistor with low dielectric core insulating layer and method of manufacturing the same
US11812613B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-11812613-B2 |
| Application number | US-202117211460-A |
| Country | US |
| Kind code | B2 |
| Filing date | Mar 24, 2021 |
| Priority date | Sep 25, 2020 |
| Publication date | Nov 7, 2023 |
| Grant date | Nov 7, 2023 |
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- Title
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Abstract
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The present technology relates to a semiconductor memory device and a method of manufacturing the same. The semiconductor memory device includes a stack with a plurality of interlayer insulating layers and a plurality of gate electrodes alternately stacked on a substrate, and a plurality of channel structures passing through the stack in a vertical direction. Each of the plurality of channel structures includes a core insulating layer, a channel layer, a tunnel insulating layer, and a charge storage layer that vertically extend in the same direction as the plurality of channel structures, and a dielectric constant of a partial region of the core insulating layer is lower than a dielectric constant of another region of the core insulating layer.
First claim
Opening claim text (preview).
What is claimed is: 1. A semiconductor memory device comprising: a stack with a plurality of interlayer insulating layers and a plurality of gate electrodes that are alternately stacked on a substrate; and a plurality of channel structures passing through the stack in a vertical direction, wherein each of the plurality of channel structures includes a core insulating layer, a channel layer, a tunnel insulating layer, and a charge storage layer that vertically extend in the same direction as the plurality of channel structures, and wherein a dielectric constant of a first region of the core insulating layer, which corresponds to a source select transistor or a drain select transistor, is lower than a dielectric constant of a second region of the core insulating layer which corresponds to memory cells. 2. The semiconductor memory device of claim 1 , wherein the first region of the core insulating layer is adjacent to a first gate electrode of the source select transistor or a second gate electrode of the drain select transistor. 3. The semiconductor memory device of claim 1 , wherein a dopant is injected into the first region of the core insulating layer. 4. The semiconductor memory device of claim 3 , wherein the dopant is carbon, fluorine, or both carbon and fluorine. 5. The semiconductor memory device of claim 1 , wherein the first region of the core insulating layer includes a gap. 6. A semiconductor memory device comprising: a stack with a plurality of interlayer insulating layers and gate electrodes alternately stacked on a substrate; and a plurality of channel structures passing through the stack in a vertical direction, wherein each of the plurality of channel structures includes a core insulating layer, a channel layer, a tunnel insulating layer, and a charge storage layer that vertically extend in the same direction as the plurality of channel structures, wherein at least one first gate electrode that is disposed at an uppermost portion of the gate electrodes corresponds to a drain select transistor, at least one second gate electrode that is disposed at a lowermost portion of the gate electrodes corresponds to a source select transistor, and remaining gate electrodes among the gate electrodes correspond to memory cells, and wherein a partial region of the core insulating layer that is adjacent to the first gate electrode or the second gate electrode has a dielectric constant that is lower than a dielectric constant of another region that is adjacent to the remaining gate electrodes. 7. The semiconductor memory device of claim 6 , wherein a dopant is injected into the partial region of the core insulating layer. 8. The semiconductor memory device of claim 7 , wherein the dopant is carbon, fluorine, or both carbon and fluorine. 9. The semiconductor memory device of claim 6 , wherein a gap is formed in the partial region of the core insulating layer.
Assignees
Inventors
Classifications
IGFETs having charge trapping gate insulators, e.g. MNOS transistors · CPC title
of FETs having charge-trapping gate insulators, e.g. MNOS transistors · CPC title
Vertical IGFETs having charge trapping gate insulators · CPC title
comprising charge-trapping insulators · CPC title
- H10B43/27Primary
the channels comprising vertical portions, e.g. U-shaped channels · CPC title
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Frequently asked questions
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- What does patent US11812613B2 cover?
- The present technology relates to a semiconductor memory device and a method of manufacturing the same. The semiconductor memory device includes a stack with a plurality of interlayer insulating layers and a plurality of gate electrodes alternately stacked on a substrate, and a plurality of channel structures passing through the stack in a vertical direction. Each of the plurality of channel st…
- Who is the assignee on this patent?
- Sk Hynix Inc
- What technology area does this patent fall under?
- Primary CPC classification H10B43/27. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Nov 07 2023 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 4 related publications on this page (citations in our corpus or others sharing the same primary CPC).