Electronic device and a method for suppressing noise for an electronic device

Patent metadata

Field	Value
Publication number	US-11811378-B2
Application number	US-201917423238-A
Country	US
Kind code	B2
Filing date	Dec 24, 2019
Priority date	Jan 16, 2019
Publication date	Nov 7, 2023
Grant date	Nov 7, 2023

Abstract

The present invention relates to an electronic device, comprising: —a GFET; —noise suppression means comprising: —a modulation unit applying to a gate (G) of the GFET a signal Vg with frequency fm to modulate charge carrier density of a graphene channel around the charge neutrality point between charge carrier density values at frequency fm, —a control unit (CU), and—a demodulation circuit which is CMOS-implemented and that: —comprises first and second circuital branches alternately switchable to demodulate an electrical signal of frequency fm; or—is configured to generate and apply a signal Vb with frequency fmb to a source (S) of the GFET continuously, simultaneously and with a delay td to induce a phase with respect to Vg to yield a maximal demodulated output signal (So). The present invention also concerns to a method for suppressing noise for the device of the invention.

First claim

The invention claimed is:

1. An electronic device, comprising:
a graphene field effect transistor (GFET); and
a noise suppression mechanism comprising a modulation unit configured to generate and apply to a gate electrode structure of said GFET, a voltage oscillating time-dependent signal having at least one component with a frequency of f m and that oscillates between first and second voltage values selected so that charge carrier density of a graphene channel of the GFET is modulated around the charge neutrality point of the graphene between charge carrier density values at, at least, said frequency f m ,
wherein said noise suppression mechanism further comprises a control unit, and a demodulation circuit which is CMOS-implemented and that comprises first and second circuital branches which are alternately switchable, under the control of said control unit, to demodulate at least an electrical signal of frequency f m of a modulated electrical current circulating through the graphene channel of the GFET when is under said modulation around the charge neutrality point of the graphene.

2. The device according to claim 1 , wherein said first and second circuital branches are alternately switchable, under the control of said control unit, for respectively sampling first and second portions of at least said electrical signal of frequency f m of a modulated electrical current circulating through the graphene channel when the GFET is biased and the graphene channel is under said modulation around the charge neutrality point of the graphene.

3. The device according to claim 2 , wherein said demodulation circuit further comprises:
a high-pass filter having a cut frequency f c1 <f m and that electrically connects an output of the GFET through which said modulated electrical current goes out, or of a further component electrically connected to said output, with an input of said demodulation circuit; and
a post-processing unit electrically connected to respective outputs of said first and second circuital branches to receive, under the control of said control unit, said sampled first and second portions, and configured to process the same to provide a demodulated output signal.

4. The device according to claim 3 , wherein said post-processing unit is configured to process said sampled first and second portions to provide said demodulated output signal according to one or more of the following types of linear combinations: additions, subtractions, or weighted additions and subtractions.

5. The device according to claim 2 , wherein each of said first and second circuital branches comprises:
a switch configured and arranged to electrically connect or disconnect said input of the demodulation circuit with the output of the respective circuital branch, when in a respective on or off state induced by said control unit; and
a capacitor electrically connected between said output of the respective circuital branch and a ground point and that is configured and arranged to be charged with an electrical current circulating through said switch when in said on state;
wherein said post-processing unit is configured to receive said sampled first and second portions by measuring, under the control of said control unit, the magnitude of the electrical charge stored on the respective charged capacitor;
and wherein the device further comprises at least one reset circuit configured and arranged to drain, under the control of the control unit, the electrical charge stored on the capacitors.

6. The device according to claim 5 , wherein said demodulation circuit further comprises said further component electrically connected between said output of the GFET and said high-pass filter, wherein said further component is a transimpedance or capacitive transimpedance amplifier.

7. The device according to claim 2 , wherein each of said first and second circuital branches comprises:
a switch configured and arranged to electrically connect or disconnect said input of the demodulation circuit with the output of the respective circuital branch, when in a respective on or off state induced by said control unit;
a capacitive transimpedance amplifier with an input electrically connected between said switch and the output of the respective circuital branch, wherein said capacitive transimpedance amplifier comprises, electrically connected in parallel with each other:
an operational amplifier,
a capacitor configured and arranged to be charged with an electrical current circulating through said switch when in said on state, and
a reset circuit configured and arranged to drain, under the control of the control unit, the electrical charge stored on the capacitor;
wherein said post-processing unit is configured to receive said sampled first and second portions by measuring, under the control of said control unit, the magnitude of the electrical signal provided by the operation amplifier when the respective capacitor is charged.

8. The device according to claim 5 , wherein said control unit is configured to control said switches, said post-processing unit, and said at least one reset circuit, to operate according to a reading mode that comprises:
inducing said on state of said switch of the first circuital branch along a time t int1 that coincides with at least part of the time during which the first voltage value of the voltage oscillating time-dependent signal is being applied to the gate electrode structure of the GFET;
inducing said off state of said switch of the first circuital branch;
inducing said on state of said switch of the second circuital branch along a time t int2 that coincides with at least part of the time during which the second voltage value of the voltage oscillating time-dependent signal is being applied to the gate electrode structure of the GFET;
inducing said off state of said switch of the second circuital branch, once said t int2 has lapsed;
controlling said at least one reset circuit or reset circuits, to drain the electrical charge stored on the capacitors, after said t int2 has lapsed;
controlling the post-processing unit to obtain a signal out by performing, and then processing, the following measurements:
during t int1 or t int2 :
the magnitude of the electrical charge stored on the charged capacitor of the first circuital branch; or
the magnitude of the electrical signal provided by the operation amplifier of the first circuital branch when the respective capacitor is charged;

during t int2 :
the magnitude of the electrical charge stored on the charged capacitor of the second circuital branch; or
the magnitude of the electrical signal provided by the operation amplifier of the second circuital branch when the respective capacitor is charged.

9. The device according to claim 1 , wherein said control unit is configured also to generate and apply to said gate electrode structure of the GFET said voltage oscillating time-dependent signal having at least one component with a frequency of f m and that oscillates between first and second voltage values.

10. The device according to claim 9 , wherein the GFET further comprises a sensitizing structure arranged over said graphene channel, wherein said sensitizing structure is configured to induce charge carriers therein, wherein said sensitizing structure is an actively controlled sensitizing or functionalizing structure, and wherein the device further comprising a drift compensation mechanism to compensate an unwanted drift caused by the graphene of the GFET, said drift compensation mechanism comprising a control electrode electrically connected to said actively controlled sensitizing structure and said control unit configured to operate in a drift compensation

Assignees

• Fundacio Inst De Ciencies Fotòniques
• Inst Catalana Recerca Estudis Avancats

Inventors

• Goossens Stijn
• Koppens Frank
• Konstantatos Gerasimos
• Monasterio Carles

Classifications

• H10D62/882

  Graphene · CPC title

• H10F30/20

  the devices having potential barriers, e.g. phototransistors · CPC title

• H10D30/60 Primary

  Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence) · CPC title

• H10D30/67

  Thin-film transistors [TFT] {(Stacked nanowire, nanosheet or nanoribbon FETs H10D30/501)} · CPC title

• H03H11/1217 Primary

  using a plurality of operational amplifiers (H03H11/1204 takes precedence; parallel-T filters H03H11/1295) · CPC title