Array substrate, driving method thereof, display panel and touch display device

US11809656B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11809656-B2
Application numberUS-201917052529-A
CountryUS
Kind codeB2
Filing dateNov 18, 2019
Priority dateOct 31, 2019
Publication dateNov 7, 2023
Grant dateNov 7, 2023

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

The array substrate at least includes a plurality of electrode rows, a plurality of switch control lines and a plurality of switch units in a display area; each electrode row corresponds to at least one switch control line, each first electrode corresponds to one switch unit, and each switch unit includes at least one first switch; and in one of the electrode rows: the control terminal of at least one first switch in each switch unit in the one electrode row is connected to the same switch control line, the first poles of the first switches connected to the same switch control line are electrically connected to the first electrodes respectively, and the second poles of the first switches connected to the same switch control line are electrically connected to one another.

First claim

Opening claim text (preview).

What is claimed is: 1. An array substrate, comprising: a display area; a non-display area surrounding the display area; a base substrate; a plurality of gate lines, extending in a first direction and arranged in a second direction; a plurality of data lines, extending in the second direction and arranged in the first direction; wherein the gate lines and the data lines intersect and define a plurality of sub-pixels, the gate lines provide switch control signals for the sub-pixels, and the data lines provide data signals for the sub-pixels; electrode rows, extending in the first direction and arranged in the second direction; wherein the electrode rows each comprises a plurality of first electrodes, the first electrodes are in the display area, and orthographic projections of at least two of the sub-pixels on a plane, where the base substrate is located, fall within an orthographic projection of a corresponding one of the first electrodes on the plane; a plurality of switch control lines; and a plurality of switch units in the display area; wherein the electrode rows each corresponds to at least one of the switch control lines, the first electrodes each corresponds to a respective one of the switch units, and the switch units each comprises at least one first switch; wherein in one of the electrode rows: a control terminal of at least one first switch in each of the switch units in the one electrode row is connected to a corresponding one of the switch control lines, first poles of first switches connected to the one switch control line are electrically connected to the first electrodes in the one electrode row respectively, and second poles of the first switches connected to the one switch control line are electrically connected to one another; and in a display stage, the first electrodes are multiplexed as common electrodes and receive common voltage signals, the one switch control line transmits a first control signal to the first switches connected to the one switch control line, and the first electrodes in the one electrode row electrically connected to the first switches are electrically connected. 2. The array substrate according to claim 1 , wherein: the electrode rows each corresponds to a respective one of the switch control lines; orthographic projections of n rows of the sub-pixels on the plane overlap with an orthographic projection of a corresponding one of the electrode rows on the plane, and n≥1; and in the display stage, during scanning of the sub-pixels overlapping with the orthographic projection of the one electrode row on the plane, the one switch control line corresponding to the one electrode row continuously transmits the first control signal to the first switches connected to the one switch control line. 3. The array substrate according to claim 2 , wherein: the switch units each comprises a plurality of first switches; and in one of the switch units, control terminals of the first switches in the one switch unit are connected to one of the switch control lines, first poles of the first switches in the one switch unit are connected to one of the first electrodes, and second poles of the first switches in the one switch unit are electrically connected to one another. 4. The array substrate according to claim 3 , wherein the first switches in the one switch unit are arranged in an array in the first direction and the second direction. 5. The array substrate according to claim 3 , wherein the first switches in the one switch unit are arranged in the first direction to form a switch row. 6. The array substrate according to claim 3 , wherein the first switches in the one switch unit are arranged in the second direction to form a switch column. 7. The array substrate according to claim 1 , wherein: orthographic projections of n rows of the sub-pixels on the plane overlap with an orthographic projection of a corresponding one of the electrode rows on the plane, and n≥2; the electrode rows each corresponds to m switch control lines, and m=n; and the gate lines are multiplexed as the switch control lines. 8. The array substrate according to claim 7 , wherein: s first switches are comprised in each of the switch units, and s≥n; and in one of the electrode rows, the control terminal of at least one first switch in each of the switch units in the one electrode row is connected to a corresponding one of the gate lines. 9. The array substrate according to claim 8 , wherein: the switch units each comprises a plurality of sub-switch units, a number of the sub-switch units is p, and p=n; and the sub-switch units each comprises a plurality of first switches; and control terminals of first switches in one of the sub-switch units are connected to a corresponding one of the switch control lines, and first switches in different sub-switch units are connected to different switch control lines. 10. The array substrate according to claim 1 , further comprising: touch electrodes; and touch signal lines electrically connected to the touch electrodes in a one-to-one correspondence; wherein in a touch stage, the first electrodes are multiplexed as the touch electrodes, the first switches are turned off, and the first electrodes receive touch detection signals. 11. A method for driving the array substrate according to claim 1 , comprising a method for driving the array substrate in the display stage, wherein, in the display stage: the first electrodes are multiplexed as the common electrodes and receive the common voltage signals; the gate lines transmit the switch control signals to sub-pixels connected to the gate lines to scan the sub-pixels; the switch control lines each transmits the first control signal to first switches connected to the switch control line; the first switches connected to the switch control line are turned on under control of the first control signal; and first electrodes in an electrode row electrically connected to the first switches are electrically connected, and potentials of the first electrodes in the electrode row are the same. 12. The method for driving the array substrate according to claim 11 , wherein: the electrode rows each corresponds to a respective one of the switch control lines; orthographic projections of n rows of the sub-pixels on the plane overlap with an orthographic projection of a corresponding one of the electrode rows on the plane, and n 1 ; and in the display stage, during scanning of the sub-pixels overlapping with the orthographic projection of the one electrode row on the plane by the gate lines, the one switch control line corresponding to the one electrode row continuously transmits the first control signal to the first switches connected to the one switch control line. 13. The method for driving the array substrate according to claim 11 , wherein: orthographic projections of n rows of the sub-pixels on the plane overlap with an orthographic projection of a corresponding one of the electrode rows on the plane, and n≥2; the electrode rows each corresponds to m switch control lines, and m=n; the gate lines are multiplexed as the switch control lines; and in the display stage, the gate lines transmit the switch control signals to the sub-pixels connected to the gate lines and transmit the first control signals to the first switches connected to the gate lines; wherein the switch control signals and the first control signals are the same signals. 14. The method for driving the array substrate according to claim 11 , further comprising a method for driving the array substrate in a touch stage, wherein: in the touch stage, the first el

Assignees

Inventors

Classifications

  • Interconnections, e.g. scanning lines · CPC title

  • wherein the TFTs are in active matrices · CPC title

  • Connections between sensors and controllers, e.g. routing lines between electrodes and connection pads · CPC title

  • G06F3/0412Primary

    Digitisers structurally integrated in a display · CPC title

  • using a grid-like structure of electrodes in at least two directions, e.g. using row and column electrodes · CPC title

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What does patent US11809656B2 cover?
The array substrate at least includes a plurality of electrode rows, a plurality of switch control lines and a plurality of switch units in a display area; each electrode row corresponds to at least one switch control line, each first electrode corresponds to one switch unit, and each switch unit includes at least one first switch; and in one of the electrode rows: the control terminal of at le…
Who is the assignee on this patent?
Xiamen Tianma Micro Electronics Co Ltd
What technology area does this patent fall under?
Primary CPC classification G06F3/04164. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Nov 07 2023 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 3 related publications on this page (citations in our corpus or others sharing the same primary CPC).