Array substrate, liquid crystal display panel and display device

Patent metadata

Field	Value
Publication number	US-11809048-B2
Application number	US-202117475045-A
Country	US
Kind code	B2
Filing date	Sep 14, 2021
Priority date	Jan 27, 2021
Publication date	Nov 7, 2023
Grant date	Nov 7, 2023

Abstract

The present disclosure discloses an array substrate, a liquid crystal display panel and a display device. The array substrate includes: a base substrate, and a first electrode and a second electrode located in a region defined by intersection of two adjacent data lines, a gate line and a common electrode signal line, where the second electrode is located on a side of the first electrode facing away from the base substrate; the first electrode is in a block shape; the second electrode has a symmetry axis perpendicular to the gate line and passing through the center of the second electrode; the second electrode includes: a frame with an opening in a side; an opening side of the frame faces a first type of signal lines; the first type of signal lines are other signal lines than the data lines and signal lines parallel to the data lines.

First claim

What is claimed is:

1. An array substrate, comprising: a base substrate, data lines located on a side of the base substrate and extending in a first direction, a gate line and a common electrode signal line extending in a second direction, and a first electrode and a second electrode located in a region defined by intersection of two adjacent data lines, the gate line and the common electrode signal line, wherein the second electrode is located on a side of the first electrode facing away from the base substrate;
the first electrode is in a block shape;
the second electrode has a symmetry axis perpendicular to the gate line and passing through a center of the second electrode; the second electrode comprises: a frame with an opening in a side, and a first group of electrode strips and a second group of electrode strips located in the frame and disposed on two sides of the symmetry axis respectively, the first group of electrode strips comprises a plurality of first sub-electrode strips connected with the frame and extending in a third direction, and the second group of electrode strips comprises a plurality of second sub-electrode strips connected with the frame and extending in a fourth direction; and an opening side of the frame faces the common electrode signal line, and the fourth direction and the third direction are different extending directions;
wherein the opening is not surrounded by the second electrode.

2. The array substrate according to claim 1 , wherein the second electrode is a common electrode, and the first electrode is a pixel electrode; or, the second electrode is a pixel electrode, and the first electrode is a common electrode.

3. The array substrate according to claim 1 , wherein the array substrate further comprises: a connecting part integrally connected with the second electrode, an orthographic projection of the connecting part on the base substrate and an orthographic projection of the common electrode signal line on the base substrate have an overlapping region, and the connecting part is connected with the common electrode signal line through perforation in the overlapping region.

4. The array substrate according to claim 3 , wherein the array substrate comprises a gate connected with the gate line, and the connecting part and the gate are located on a same side of the second electrode.

5. The array substrate according to claim 4 , wherein in a direction parallel to the base substrate and perpendicular to the gate line, a width of the connecting part is greater than a width of the common electrode signal line.

6. The array substrate according to claim 1 , wherein a distance between each first sub-electrode strip and the symmetry axis gradually increases from an end close to the opening side of the frame to an end close to an opposite side of the opening of the frame.

7. The array substrate according to claim 6 , wherein at least a part of the first group of electrode strips and/or at least a part of the second group of electrode strips extends to the opening side of the frame.

8. The array substrate according to claim 7 , wherein an edge of the electrode strip extending to the opening side is substantially flush with an edge of the frame at the opening side.

9. The array substrate according to claim 7 , wherein the first group of electrode strips and the second group of electrode strips all extend to the opening side of the frame.

10. The array substrate according to claim 1 , wherein a shape of the frame is a rectangle, and long edges of the rectangle are parallel to the gate line.

11. A liquid crystal display panel, comprising an array substrate, wherein the array substrate comprises: a base substrate, data lines located on a side of the base substrate and extending in a first direction, a gate line and a common electrode signal line extending in a second direction, and a first electrode and a second electrode located in a region defined by intersection of two adjacent data lines, the gate line and the common electrode signal line, wherein the second electrode is located on a side of the first electrode facing away from the base substrate;
the first electrode is in a block shape;
the second electrode has a symmetry axis perpendicular to the gate line and passing through a center of the second electrode; the second electrode comprises: a frame with an opening in a side, and a first group of electrode strips and a second group of electrode strips located in the frame and disposed on two sides of the symmetry axis respectively, the first group of electrode strips comprises a plurality of first sub-electrode strips connected with the frame and extending in a third direction, and the second group of electrode strips comprises a plurality of second sub-electrode strips connected with the frame and extending in a fourth direction; and an opening side of the frame faces the common electrode signal line, and the fourth direction and the third direction are different extending directions;
wherein the opening is not surrounded by the second electrode.

12. The liquid crystal display panel according to claim 11 , wherein the second electrode is a common electrode, and the first electrode is a pixel electrode; or, the second electrode is a pixel electrode, and the first electrode is a common electrode.

13. The liquid crystal display panel according to claim 11 , wherein the array substrate further comprises: a connecting part integrally connected with the second electrode, an orthographic projection of the connecting part on the base substrate and an orthographic projection of the common electrode signal line on the base substrate have an overlapping region, and the connecting part is connected with the common electrode signal line through perforation in the overlapping region.

14. The liquid crystal display panel according to claim 13 , wherein the array substrate comprises a gate connected with the gate line, and the connecting part and the gate are located on a same side of the second electrode.

15. The liquid crystal display panel according to claim 14 , wherein in a direction parallel to the base substrate and perpendicular to the gate line, a width of the connecting part is greater than a width of the common electrode signal line.

16. The liquid crystal display panel according to claim 11 , wherein a distance between each first sub-electrode strip and the symmetry axis gradually increases from an end close to the opening side of the frame to an end close to an opposite side of the opening of the frame.

17. The liquid crystal display panel according to claim 11 , wherein a shape of the frame is a rectangle, and long edges of the rectangle are parallel to the gate line.

18. A display device, comprising a liquid crystal display panel, wherein the liquid crystal display panel comprises an array substrate, and the array substrate comprises: a base substrate, data lines located on a side of the base substrate and extending in a first direction, a gate line and a common electrode signal line extending in a second direction, and a first electrode and a second electrode located in a region defined by intersection of two adjacent data lines, the gate line and the common electrode signal line, wherein the second electrode is located on a side of the first electrode facing away from the base substrate;
the first electrode is in a block shape;
the second electrode has a symmetry axis perpendicular to the gate line and passing through a center of the second electrode; the second electrode comprises: a frame with an opening in a side, and a first group of electro

Assignees

• Boe Technology Group Co Ltd

Inventors

• Choi Hyunsic

Classifications

• G02F1/134309 Primary

  characterised by their geometrical arrangement · CPC title

• G02F1/13439

  characterised by their electrical, optical, physical properties; materials therefor; method of making · CPC title

• G02F1/136286

  Wiring, e.g. gate line, drain line · CPC title

• G02F1/133707 Primary

  Structures for producing distorted electric fields, e.g. bumps, protrusions, recesses, slits in pixel electrodes · CPC title

• G02F1/1362

  Active matrix addressed cells {(G02F1/134336, G02F1/134363 take precedence)} · CPC title