Fractional frequency synthesis by sigma-delta modulating frequency of a reference clock

Patent metadata

Field	Value
Publication number	US-11804847-B2
Application number	US-201816205308-A
Country	US
Kind code	B2
Filing date	Nov 30, 2018
Priority date	Nov 30, 2018
Publication date	Oct 31, 2023
Grant date	Oct 31, 2023

Abstract

A circuit includes a programmable frequency divider which receives a high-speed clock, f in , as an input and which provides a modulated reference clock as an output; a Sigma-Delta modulator which receives a Frequency Control Word (FCW) and which is connected to the programmable frequency divider to receive the modulated reference clock as a sample clock and to control an average frequency of the modulated reference clock; and an integer-N Phase Lock Loop (PLL) which receives the modulated reference clock and outputs a clock output.

First claim

What is claimed is:

1. A circuit comprising:
a Digital-Analog Converter (DAC) Phase Lock Loop (PLL) which receives a reference clock and generates a high-speed clock, f in , wherein the DAC PLL and the high-speed clock, f in , are for an optical transmitter of a high-speed optical transceiver or modem; and
a clock frequency modulator device configured to receive the high-speed clock, f in , which is reused from the optical transmitter for a client side of the high-speed optical transceiver or modem, wherein the clock frequency modulator device includes
a programmable frequency divider which receives the high-speed clock, f in , as an input from the DAC PLL and provides a modulated reference clock as an output;
a Sigma-Delta modulator which receives a Frequency Control Word (FCW) and which is connected to the programmable frequency divider to receive the modulated reference clock as a sample clock, the Sigma-Delta modulator configured to provide the FCW to the programmable frequency divider to control an average frequency of the modulated reference clock provided as the output of the programmable frequency divider, wherein the FCW is set based on tracking the client side, thereby reusing the high-speed clock, f in , for both the transmitter and the client side of the high-speed optical transceiver or modem; and
an integer-N Phase Lock Loop (PLL) that operates at an integer value and which receives the modulated reference clock and outputs a clock output;

wherein the circuit achieves fractional-N frequency synthesis without the use of a fractional-N PLL.

2. The circuit of claim 1 , wherein an average frequency of the modulated reference clock is equal to

f
in

I
+
FCW

,

and wherein the frequency of the clock output is equal to

f
in

⁢

M

I
+
FCW

,

where M is a divisor ratio set by the programmable frequency divider, and where I is an integer divisor.

3. The circuit of claim 1 , wherein an integer divisor (I) is provided to the programmable frequency divider with the FCW, wherein the programmable frequency divider and Sigma-Delta modulator are configured to perform a Numerically Controlled Oscillator (NCO) function based on selected values for the FCW, the integer divisor (I), and the integer-N PLL, and wherein the circuit drives a Serializer/Deserializer (SerDes).

4. The circuit of claim 1 , wherein the FCW defines a numerator value for the programmable frequency divider, and wherein a denominator value for the programmable frequency divider is set by one of i) rail voltages for an analog Sigma-Delta modulator and ii) a number of accumulator bits for a digital Sigma-Delta modulator.

5. The circuit of claim 1 , wherein the circuit is disposed in an Application Specific Integrated Circuit (ASIC) on a Printed Circuit Board (PCB).

6. The circuit of claim 5 , wherein the DAC PLL is disposed on the ASIC which receives the reference clock from the PCB.

7. An apparatus comprising:
a Printed Circuit Board (PCB) with a reference clock;
a circuit including:
a Digital-Analog Converter (DAC) Phase Lock Loop (PLL) configured to receive the reference clock and provide a high-speed clock, f in , wherein the DAC PLL and the high-speed clock, f in , are for an optical transmitter of a high-speed optical transceiver or modem; and
a clock frequency modulator device configured to receive the high-speed clock, f in , which is reused from the optical transmitter for a client side of the high-speed optical transceiver or modem, wherein the clock frequency modulator device includes
a programmable frequency divider which receives the high-speed clock, f in , as an input from the DAC PLL and provides a modulated reference clock as an output;
a Sigma-Delta modulator which receives a Frequency Control Word (FCW) and which is connected to the programmable frequency divider to receive the modulated reference clock as a sample clock, the Sigma-Delta modulator configured to provide the FCW to the programmable frequency divider to control an average frequency of the modulated reference clock provided as the output of the programmable frequency divider, wherein the FCW is set based on tracking the client side, thereby reusing the high-speed clock, f in , for both the transmitter and the client side of the high-speed optical transceiver or modem; and
an integer-N PLL that operates at an integer value and which receives the modulated reference clock and outputs a clock output;

wherein the circuit achieves fractional-N frequency synthesis without the use of a fractional-N PLL.

8. The apparatus of claim 7 , wherein an average frequency of the modulated reference clock is equal to

f
in

I
+
FCW

,

and wherein the frequency of the clock output is equal to

f
in

⁢

M

I
+
FCW

,

where M is a divisor ratio set by the programmable frequency divider, and where I is an integer divisor.

9. The apparatus of claim 7 , wherein an integer divisor (I) is provided to the programmable frequency divider with the FCW, wherein the programmable frequency divider and Sigma-Delta modulator are configured to perform a Numerically Controlled Oscillator (NCO) function based on selected values for the FCW, the integer divisor (I), and the integer-N PLL, and wherein the circuit drives a Serializer/Deserializer (SerDes).

10. The apparatus of claim 7 , wherein the FCW defines a numerator value for the programmable frequency divider, and wherein a denominator value for the programmable frequency divider is set by one of i) rail voltages for an analog Sigma-Delta modulator and ii) a number of accumulator bits for a digital Sigma-Delta modulator.

11. A method of operating a circuit comprising:
generating a high-speed clock, f in , from a Digital-Analog Converter (DAC) Phase Lock Loop (PLL), wherein the DAC PLL and the high-speed clock, f in , are in for an optical transmitter of a high-speed optical transceiver or modem;
receiving the high-speed clock, f in , as an input to a programmable frequency divider, wherein the high-speed clock, f in , is reused from the optical transmitter for a client side of the high-speed optical transceiver or modem by a clock frequency modulator device that performs steps of
modulating the high-speed clock, f in , with a Sigma-Delta modulator and providing a Frequency Control Word (FCW) to the programmable frequency divider to control an av

Assignees

• Ciena Corp

Inventors

• Aouini Sadok
• Mikkelsen Matthew
• Ben-Hamida Naim
• Parvizi Mahdi
• Wen Tingjun
• Plett Calvin

Classifications

• H03L7/1976 Primary

  using a phase accumulator for controlling the counter or frequency divider · CPC title

• H03L7/18 Primary

  using a frequency divider or counter in the loop (H03L7/20, H03L7/22 take precedence) · CPC title

• H03L7/22

  using more than one loop · CPC title